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Searched refs:GC_HWIP (Results 1 - 25 of 63) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15_common.h84 uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0; \
85 uint32_t r1 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1; \
86 uint32_t spare_int = adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT; \
107 uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2; \
108 uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3; \
109 uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; \
110 uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; \
123 uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\
H A Dnavi12_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in navi12_reg_base_init()
H A Dnavi14_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in navi14_reg_base_init()
H A Dnavi10_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in navi10_reg_base_init()
H A Dsienna_cichlid_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in sienna_cichlid_reg_base_init()
H A Darct_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
H A Dvega20_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
H A Dvega10_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15_common.h111 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP, 0)
118 uint32_t r0 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0; \
119 uint32_t r1 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1; \
120 uint32_t spare_int = adev->reg_offset[GC_HWIP][inst][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SPARE_INT; \
139 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP, inst)
143 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)
155 uint32_t r2 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2; \
156 uint32_t r3 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3; \
157 uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_GFX_CNTL; \
158 uint32_t grbm_idx = adev->reg_offset[GC_HWIP][ins
[all...]
H A Dgmc_v9_0.c642 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) in gmc_v9_0_process_interrupt()
656 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) in gmc_v9_0_process_interrupt()
773 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || in gmc_v9_0_use_invalidate_semaphore()
774 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) in gmc_v9_0_use_invalidate_semaphore()
825 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)) { in gmc_v9_0_flush_gpu_tlb()
835 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) && in gmc_v9_0_flush_gpu_tlb()
897 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) in gmc_v9_0_flush_gpu_tlb()
970 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)); in gmc_v9_0_flush_gpu_tlb_pasid()
985 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) && in gmc_v9_0_flush_gpu_tlb_pasid()
1193 switch (adev->ip_versions[GC_HWIP][ in gmc_v9_0_get_coherence_flags()
[all...]
H A Dgmc_v10_0.c148 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) in gmc_v10_0_process_interrupt()
246 GC_HWIP : MMHUB_HWIP; in gmc_v10_0_flush_vm_hub()
281 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) in gmc_v10_0_flush_vm_hub()
714 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_set_gfxhub_funcs()
828 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_mc_init()
895 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_sw_init()
913 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_sw_init()
1221 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 3) || in gmc_v10_0_get_clockgating_state()
1222 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 4)) in gmc_v10_0_get_clockgating_state()
H A Damdgpu_discovery.c181 [GC_HWIP] = GC_HWID,
327 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) { in amdgpu_discovery_harvest_config_quirk()
1378 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0) && in amdgpu_discovery_harvest_ip()
1379 adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 3)) { in amdgpu_discovery_harvest_ip()
1622 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_common_ip_blocks()
1658 "Failed to add common ip block(GC_HWIP:0x%x)\n", in amdgpu_discovery_set_common_ip_blocks()
1659 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_common_ip_blocks()
1668 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_gmc_ip_blocks()
1704 "Failed to add gmc ip block(GC_HWIP:0x%x)\n", in amdgpu_discovery_set_gmc_ip_blocks()
1705 adev->ip_versions[GC_HWIP][ in amdgpu_discovery_set_gmc_ip_blocks()
[all...]
H A Daldebaran_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in aldebaran_reg_base_init()
H A Ddimgrey_cavefish_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
H A Dgfx_v9_0.c898 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_init_golden_registers()
954 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && in gfx_v9_0_init_golden_registers()
955 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2))) in gfx_v9_0_init_golden_registers()
1098 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && in gfx_v9_0_check_fw_write_wait()
1105 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_check_fw_write_wait()
1205 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) && in check_if_enlarge_doorbell_range()
1218 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_check_if_need_gfxoff()
1329 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || in gfx_v9_0_load_mec2_fw_bin_support()
1330 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || in gfx_v9_0_load_mec2_fw_bin_support()
1331 adev->ip_versions[GC_HWIP][ in gfx_v9_0_load_mec2_fw_bin_support()
[all...]
H A Dmes_v10_1.c304 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; in mes_v10_1_set_hw_resources()
561 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_load_microcode()
571 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_load_microcode()
581 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_load_microcode()
590 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_load_microcode()
998 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_kiq_setting()
H A Darct_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
H A Dpsp_v10_0.c61 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 1, 0)) && in psp_v10_0_init_microcode()
H A Dvega20_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
H A Dvega10_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
H A Damdgpu_display.c766 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) in convert_tiling_flags_to_modifier()
768 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) in convert_tiling_flags_to_modifier()
770 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0)) in convert_tiling_flags_to_modifier()
779 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { in convert_tiling_flags_to_modifier()
785 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { in convert_tiling_flags_to_modifier()
841 adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0); in convert_tiling_flags_to_modifier()
878 if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) && in convert_tiling_flags_to_modifier()
H A Dgfx_v10_0.c3630 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_spm_golden_registers()
3653 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_golden_registers()
3894 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_check_fw_write_wait()
3945 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_check_gfxoff_flag()
3967 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) && in gfx_v10_0_init_microcode()
3970 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); in gfx_v10_0_init_microcode()
4142 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_rlcg_reg_access_ctrl()
4356 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_gpu_early_init()
4489 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_sw_init()
4747 if (((adev->ip_versions[GC_HWIP][ in gfx_v10_0_setup_rb()
[all...]
H A Dgmc_v11_0.c207 GC_HWIP : MMHUB_HWIP; in gmc_v11_0_flush_vm_hub()
628 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v11_0_set_gfxhub_funcs()
778 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v11_0_sw_init()
H A Damdgpu_ucode.c1210 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) in amdgpu_ucode_legacy_naming()
1222 } else if (block_type == GC_HWIP) { in amdgpu_ucode_legacy_naming()
1223 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_ucode_legacy_naming()
1285 case GC_HWIP: in amdgpu_ucode_ip_version_decode()
H A Damdgpu_gmc.c587 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_gmc_tmz_set()
651 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; in amdgpu_gmc_noretry_set()

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