FIELD32 (reference) in projects: kernel

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Searched refs:FIELD32 (Results 1 - 18 of 18) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/wireless/ralink/rt2x00/
H A D	rt2500pci.h	`66 #define CSR0_REVISION FIELD32(0x0000ffff) 75 #define CSR1_SOFT_RESET FIELD32(0x00000001) 76 #define CSR1_BBP_RESET FIELD32(0x00000002) 77 #define CSR1_HOST_READY FIELD32(0x00000004) 88 #define CSR3_BYTE0 FIELD32(0x000000ff) 89 #define CSR3_BYTE1 FIELD32(0x0000ff00) 90 #define CSR3_BYTE2 FIELD32(0x00ff0000) 91 #define CSR3_BYTE3 FIELD32(0xff000000) 97 #define CSR4_BYTE4 FIELD32(0x000000ff) 98 #define CSR4_BYTE5 FIELD32( [all...]`
H A D	rt2400pci.h	`55 #define CSR0_REVISION FIELD32(0x0000ffff) 64 #define CSR1_SOFT_RESET FIELD32(0x00000001) 65 #define CSR1_BBP_RESET FIELD32(0x00000002) 66 #define CSR1_HOST_READY FIELD32(0x00000004) 77 #define CSR3_BYTE0 FIELD32(0x000000ff) 78 #define CSR3_BYTE1 FIELD32(0x0000ff00) 79 #define CSR3_BYTE2 FIELD32(0x00ff0000) 80 #define CSR3_BYTE3 FIELD32(0xff000000) 86 #define CSR4_BYTE4 FIELD32(0x000000ff) 87 #define CSR4_BYTE5 FIELD32( [all...]`
H A D	rt61pci.h	63 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x0000007f) 64 #define HOST_CMD_CSR_INTERRUPT_MCU FIELD32(0x00000080) 73 #define MCU_CNTL_CSR_SELECT_BANK FIELD32(0x00000001) 74 #define MCU_CNTL_CSR_RESET FIELD32(0x00000002) 75 #define MCU_CNTL_CSR_READY FIELD32(0x00000004) 82 #define SOFT_RESET_CSR_FORCE_CLOCK_ON FIELD32(0x00000002) 88 #define MCU_INT_SOURCE_CSR_0 FIELD32(0x00000001) 89 #define MCU_INT_SOURCE_CSR_1 FIELD32(0x00000002) 90 #define MCU_INT_SOURCE_CSR_2 FIELD32(0x00000004) 91 #define MCU_INT_SOURCE_CSR_3 FIELD32( [all...]
H A D	rt73usb.h	`132 #define MAC_CSR0_REVISION FIELD32(0x0000000f) 133 #define MAC_CSR0_CHIPSET FIELD32(0x000ffff0) 142 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001) 143 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002) 144 #define MAC_CSR1_HOST_READY FIELD32(0x00000004) 150 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff) 151 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00) 152 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000) 153 #define MAC_CSR2_BYTE3 FIELD32(0xff000000) 164 #define MAC_CSR3_BYTE4 FIELD32( [all...]`
H A D	rt2800.h	`130 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001) 131 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002) 132 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004) 133 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008) 134 #define E2PROM_CSR_TYPE FIELD32(0x00000030) 135 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040) 136 #define E2PROM_CSR_RELOAD FIELD32(0x00000080) 142 #define AUX_OPT_BIT0 FIELD32(0x00000001) 143 #define AUX_OPT_BIT1 FIELD32(0x00000002) 144 #define AUX_OPT_BIT2 FIELD32( [all...]`
H A D	rt2800usb.h	46 #define TXINFO_W0_USB_DMA_TX_PKT_LEN FIELD32(0x0000ffff) 47 #define TXINFO_W0_WIV FIELD32(0x01000000) 48 #define TXINFO_W0_QSEL FIELD32(0x06000000) 49 #define TXINFO_W0_SW_USE_LAST_ROUND FIELD32(0x08000000) 50 #define TXINFO_W0_USB_DMA_NEXT_VALID FIELD32(0x40000000) 51 #define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000) 61 #define RXINFO_W0_USB_DMA_RX_PKT_LEN FIELD32(0x0000ffff) 78 #define RXD_W0_BA FIELD32(0x00000001) 79 #define RXD_W0_DATA FIELD32(0x00000002) 80 #define RXD_W0_NULLDATA FIELD32( [all...]
H A D	rt2800mmio.h	`42 #define TXD_W0_SD_PTR0 FIELD32(0xffffffff) 47 #define TXD_W1_SD_LEN1 FIELD32(0x00003fff) 48 #define TXD_W1_LAST_SEC1 FIELD32(0x00004000) 49 #define TXD_W1_BURST FIELD32(0x00008000) 50 #define TXD_W1_SD_LEN0 FIELD32(0x3fff0000) 51 #define TXD_W1_LAST_SEC0 FIELD32(0x40000000) 52 #define TXD_W1_DMA_DONE FIELD32(0x80000000) 57 #define TXD_W2_SD_PTR1 FIELD32(0xffffffff) 65 #define TXD_W3_WIV FIELD32(0x01000000) 66 #define TXD_W3_QSEL FIELD32( [all...]`
H A D	rt2500usb.h	`620 #define RF1_TUNER FIELD32(0x00020000) 625 #define RF3_TUNER FIELD32(0x00000100) 626 #define RF3_TXPOWER FIELD32(0x00003e00) 758 #define TXD_W0_PACKET_ID FIELD32(0x0000000f) 759 #define TXD_W0_RETRY_LIMIT FIELD32(0x000000f0) 760 #define TXD_W0_MORE_FRAG FIELD32(0x00000100) 761 #define TXD_W0_ACK FIELD32(0x00000200) 762 #define TXD_W0_TIMESTAMP FIELD32(0x00000400) 763 #define TXD_W0_OFDM FIELD32(0x00000800) 764 #define TXD_W0_NEW_SEQ FIELD32( [all...]`
H A D	rt2x00reg.h	`227 #define FIELD32(__mask) \ macro`
/kernel/linux/linux-6.6/drivers/net/wireless/ralink/rt2x00/
H A D	rt2500pci.h	`66 #define CSR0_REVISION FIELD32(0x0000ffff) 75 #define CSR1_SOFT_RESET FIELD32(0x00000001) 76 #define CSR1_BBP_RESET FIELD32(0x00000002) 77 #define CSR1_HOST_READY FIELD32(0x00000004) 88 #define CSR3_BYTE0 FIELD32(0x000000ff) 89 #define CSR3_BYTE1 FIELD32(0x0000ff00) 90 #define CSR3_BYTE2 FIELD32(0x00ff0000) 91 #define CSR3_BYTE3 FIELD32(0xff000000) 97 #define CSR4_BYTE4 FIELD32(0x000000ff) 98 #define CSR4_BYTE5 FIELD32( [all...]`
H A D	rt2400pci.h	`55 #define CSR0_REVISION FIELD32(0x0000ffff) 64 #define CSR1_SOFT_RESET FIELD32(0x00000001) 65 #define CSR1_BBP_RESET FIELD32(0x00000002) 66 #define CSR1_HOST_READY FIELD32(0x00000004) 77 #define CSR3_BYTE0 FIELD32(0x000000ff) 78 #define CSR3_BYTE1 FIELD32(0x0000ff00) 79 #define CSR3_BYTE2 FIELD32(0x00ff0000) 80 #define CSR3_BYTE3 FIELD32(0xff000000) 86 #define CSR4_BYTE4 FIELD32(0x000000ff) 87 #define CSR4_BYTE5 FIELD32( [all...]`
H A D	rt61pci.h	63 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x0000007f) 64 #define HOST_CMD_CSR_INTERRUPT_MCU FIELD32(0x00000080) 73 #define MCU_CNTL_CSR_SELECT_BANK FIELD32(0x00000001) 74 #define MCU_CNTL_CSR_RESET FIELD32(0x00000002) 75 #define MCU_CNTL_CSR_READY FIELD32(0x00000004) 82 #define SOFT_RESET_CSR_FORCE_CLOCK_ON FIELD32(0x00000002) 88 #define MCU_INT_SOURCE_CSR_0 FIELD32(0x00000001) 89 #define MCU_INT_SOURCE_CSR_1 FIELD32(0x00000002) 90 #define MCU_INT_SOURCE_CSR_2 FIELD32(0x00000004) 91 #define MCU_INT_SOURCE_CSR_3 FIELD32( [all...]
H A D	rt73usb.h	`132 #define MAC_CSR0_REVISION FIELD32(0x0000000f) 133 #define MAC_CSR0_CHIPSET FIELD32(0x000ffff0) 142 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001) 143 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002) 144 #define MAC_CSR1_HOST_READY FIELD32(0x00000004) 150 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff) 151 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00) 152 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000) 153 #define MAC_CSR2_BYTE3 FIELD32(0xff000000) 164 #define MAC_CSR3_BYTE4 FIELD32( [all...]`
H A D	rt2800.h	`130 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001) 131 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002) 132 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004) 133 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008) 134 #define E2PROM_CSR_TYPE FIELD32(0x00000030) 135 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040) 136 #define E2PROM_CSR_RELOAD FIELD32(0x00000080) 142 #define AUX_OPT_BIT0 FIELD32(0x00000001) 143 #define AUX_OPT_BIT1 FIELD32(0x00000002) 144 #define AUX_OPT_BIT2 FIELD32( [all...]`
H A D	rt2800usb.h	46 #define TXINFO_W0_USB_DMA_TX_PKT_LEN FIELD32(0x0000ffff) 47 #define TXINFO_W0_WIV FIELD32(0x01000000) 48 #define TXINFO_W0_QSEL FIELD32(0x06000000) 49 #define TXINFO_W0_SW_USE_LAST_ROUND FIELD32(0x08000000) 50 #define TXINFO_W0_USB_DMA_NEXT_VALID FIELD32(0x40000000) 51 #define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000) 61 #define RXINFO_W0_USB_DMA_RX_PKT_LEN FIELD32(0x0000ffff) 78 #define RXD_W0_BA FIELD32(0x00000001) 79 #define RXD_W0_DATA FIELD32(0x00000002) 80 #define RXD_W0_NULLDATA FIELD32( [all...]
H A D	rt2800mmio.h	`42 #define TXD_W0_SD_PTR0 FIELD32(0xffffffff) 47 #define TXD_W1_SD_LEN1 FIELD32(0x00003fff) 48 #define TXD_W1_LAST_SEC1 FIELD32(0x00004000) 49 #define TXD_W1_BURST FIELD32(0x00008000) 50 #define TXD_W1_SD_LEN0 FIELD32(0x3fff0000) 51 #define TXD_W1_LAST_SEC0 FIELD32(0x40000000) 52 #define TXD_W1_DMA_DONE FIELD32(0x80000000) 57 #define TXD_W2_SD_PTR1 FIELD32(0xffffffff) 65 #define TXD_W3_WIV FIELD32(0x01000000) 66 #define TXD_W3_QSEL FIELD32( [all...]`
H A D	rt2500usb.h	`620 #define RF1_TUNER FIELD32(0x00020000) 625 #define RF3_TUNER FIELD32(0x00000100) 626 #define RF3_TXPOWER FIELD32(0x00003e00) 758 #define TXD_W0_PACKET_ID FIELD32(0x0000000f) 759 #define TXD_W0_RETRY_LIMIT FIELD32(0x000000f0) 760 #define TXD_W0_MORE_FRAG FIELD32(0x00000100) 761 #define TXD_W0_ACK FIELD32(0x00000200) 762 #define TXD_W0_TIMESTAMP FIELD32(0x00000400) 763 #define TXD_W0_OFDM FIELD32(0x00000800) 764 #define TXD_W0_NEW_SEQ FIELD32( [all...]`
H A D	rt2x00reg.h	`227 #define FIELD32(__mask) \ macro`

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