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Searched refs:ENABLE_REG_32BIT (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/arch/arm/mach-omap1/
H A Dclock_data.c96 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
109 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
421 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
441 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
460 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
479 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
499 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
511 .flags = ENABLE_REG_32BIT,
521 .flags = ENABLE_REG_32BIT,
532 .flags = ENABLE_REG_32BIT,
[all...]
H A Dclock.c460 if (clk->flags & ENABLE_REG_32BIT) { in omap1_clk_enable_generic()
481 if (clk->flags & ENABLE_REG_32BIT) { in omap1_clk_disable_generic()
594 if (clk->flags & ENABLE_REG_32BIT) in omap1_clk_disable_unused()
H A Dclock.h90 #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ macro
/kernel/linux/linux-6.6/arch/arm/mach-omap1/
H A Dclock_data.c98 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT,
108 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
368 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
388 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
404 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
421 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
441 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
453 .flags = ENABLE_REG_32BIT,
463 .flags = ENABLE_REG_32BIT,
474 .flags = ENABLE_REG_32BIT,
[all...]
H A Dclock.h58 #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ macro
H A Dclock.c193 if (clk->flags & ENABLE_REG_32BIT) in omap1_clk_is_enabled()
552 if (clk->flags & ENABLE_REG_32BIT) { in omap1_clk_enable_generic()
597 if (clk->flags & ENABLE_REG_32BIT) { in omap1_clk_disable_generic()
/kernel/linux/linux-5.10/include/linux/clk/
H A Dti.h171 * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
186 #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ macro
/kernel/linux/linux-6.6/include/linux/clk/
H A Dti.h185 * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
200 #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ macro

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