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Searched refs:DSPCNTR (Results 1 - 16 of 16) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Di9xx_plane.c492 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_plane_update_arm()
524 * DSPCNTR pipe gamma enable on g4x+ and pipe csc in i9xx_plane_disable_arm()
535 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_plane_disable_arm()
557 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in g4x_primary_async_flip()
681 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_plane_get_hw_state()
1004 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_get_initial_plane_config()
H A Dintel_display.c1427 /* update DSPCNTR to configure gamma for pipe bottom color */ in ilk_crtc_enable()
1600 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ in hsw_crtc_enable()
1960 /* update DSPCNTR to configure gamma for pipe bottom color */ in valleyview_crtc_enable()
2000 /* update DSPCNTR to configure gamma for pipe bottom color */ in i9xx_crtc_enable()
2880 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_get_pipe_color_config()
7967 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); in i830_disable_pipe()
7969 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); in i830_disable_pipe()
7971 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); in i830_disable_pipe()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c187 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; in emulate_monitor_status_change()
498 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; in emulate_monitor_status_change()
H A Dfb_decoder.c213 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); in intel_vgpu_decode_primary_plane()
H A Dhandlers.c769 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) in pri_surf_mmio_write()
2085 MMIO_D(DSPCNTR(PIPE_A), D_ALL); in init_generic_mmio_info()
2096 MMIO_D(DSPCNTR(PIPE_B), D_ALL); in init_generic_mmio_info()
2107 MMIO_D(DSPCNTR(PIPE_C), D_ALL); in init_generic_mmio_info()
H A Dcmd_parser.c1279 info->ctrl_reg = DSPCNTR(info->pipe); in gen8_decode_mi_display_flip()
1345 info->ctrl_reg = DSPCNTR(info->pipe); in skl_decode_mi_display_flip()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c192 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
503 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
H A Dfb_decoder.c214 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); in intel_vgpu_decode_primary_plane()
H A Dcmd_parser.c1316 info->ctrl_reg = DSPCNTR(info->pipe); in gen8_decode_mi_display_flip()
1382 info->ctrl_reg = DSPCNTR(info->pipe); in skl_decode_mi_display_flip()
H A Dhandlers.c1020 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) in pri_surf_mmio_write()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c160 MMIO_D(DSPCNTR(PIPE_A)); in iterate_generic_mmio()
169 MMIO_D(DSPCNTR(PIPE_B)); in iterate_generic_mmio()
178 MMIO_D(DSPCNTR(PIPE_C)); in iterate_generic_mmio()
H A Dintel_clock_gating.c145 intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(pipe), 0, DISP_TRICKLE_FEED_DISABLE); in g4x_disable_trickle_feed()
H A Di915_reg.h3158 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) macro
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_display.c4481 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_update_plane()
4501 * DSPCNTR pipe gamma enable on g4x+ and pipe csc in i9xx_disable_plane()
4514 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_disable_plane()
4543 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_plane_get_hw_state()
6977 /* update DSPCNTR to configure gamma for pipe bottom color */ in ilk_crtc_enable()
7131 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ in hsw_crtc_enable()
7516 /* update DSPCNTR to configure gamma for pipe bottom color */ in valleyview_crtc_enable()
7572 /* update DSPCNTR to configure gamma for pipe bottom color */ in i9xx_crtc_enable()
9331 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_get_initial_plane_config()
9450 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plan in i9xx_get_pipe_color_config()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Dintel_pm.c1093 * DSPCNTR[13] supposedly controls whether the in g4x_plane_fifo_size()
1099 * that either DSPCNTR[13] doesn't do anything, or that in g4x_plane_fifo_size()
6878 I915_WRITE(DSPCNTR(pipe), in g4x_disable_trickle_feed()
6879 I915_READ(DSPCNTR(pipe)) | in g4x_disable_trickle_feed()
H A Di915_reg.h6529 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) macro

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