Home
last modified time | relevance | path

Searched refs:CMD2 (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/video/backlight/
H A Dtdo24m.c43 #define CMD2(x, x1, x2) ((2 << 30) | ((x) << 18) | 0x20000 |\ macro
57 CMD2(0xB8, 0xFF, 0xF9), /* Output Control */
65 CMD2(0xB8, 0x80, 0x02), /* Output Control */
91 CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
93 CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
94 CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
95 CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
104 CMD2(0xd7, 0x08, 0x04), /* Blanking period control (2) */
106 CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
107 CMD2(
[all...]
/kernel/linux/linux-6.6/drivers/video/backlight/
H A Dtdo24m.c43 #define CMD2(x, x1, x2) ((2 << 30) | ((x) << 18) | 0x20000 |\ macro
57 CMD2(0xB8, 0xFF, 0xF9), /* Output Control */
65 CMD2(0xB8, 0x80, 0x02), /* Output Control */
91 CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
93 CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
94 CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
95 CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
104 CMD2(0xd7, 0x08, 0x04), /* Blanking period control (2) */
106 CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
107 CMD2(
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/amd/
H A Damd8111e.c466 writel( REX_UFLO, mmio + CMD2); in amd8111e_restart()
468 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2); in amd8111e_restart()
470 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2); in amd8111e_restart()
477 writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 ); in amd8111e_restart()
524 /* Clear CMD2 */ in amd8111e_init_hw_default()
525 writel(CMD2_CLEAR, mmio +CMD2); in amd8111e_init_hw_default()
583 readl(mmio + CMD2); in amd8111e_init_hw_default()
1311 buf[5] = readl(mmio + CMD2); in amd8111e_read_regs()
1333 writel( VAL2 | PROM, lp->mmio + CMD2); in amd8111e_set_multicast_list()
1337 writel( PROM, lp->mmio + CMD2); in amd8111e_set_multicast_list()
[all...]
H A Damd8111e.h30 Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.
47 #define CMD2 0x50 /* Command2 register */ macro
/kernel/linux/linux-6.6/drivers/net/ethernet/amd/
H A Damd8111e.c465 writel(REX_UFLO, mmio + CMD2); in amd8111e_restart()
467 writel(VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2); in amd8111e_restart()
469 writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2); in amd8111e_restart()
476 writel(VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2); in amd8111e_restart()
523 /* Clear CMD2 */ in amd8111e_init_hw_default()
524 writel(CMD2_CLEAR, mmio + CMD2); in amd8111e_init_hw_default()
582 readl(mmio + CMD2); in amd8111e_init_hw_default()
1303 buf[5] = readl(mmio + CMD2); in amd8111e_read_regs()
1325 writel(VAL2 | PROM, lp->mmio + CMD2); in amd8111e_set_multicast_list()
1329 writel(PROM, lp->mmio + CMD2); in amd8111e_set_multicast_list()
[all...]
H A Damd8111e.h30 Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.
47 #define CMD2 0x50 /* Command2 register */ macro

Completed in 11 milliseconds