Searched refs:CMD0 (Results 1 - 6 of 6) sorted by relevance
| /kernel/linux/linux-5.10/drivers/video/backlight/ |
| H A D | tdo24m.c | 41 #define CMD0(x) ((0 << 30) | (x)) macro
48 CMD0(0x1), /* reset */
49 CMD0(0x0), /* nop */
50 CMD0(0x0), /* nop */
51 CMD0(0x0), /* nop */
56 CMD0(0x29), /* Display ON */
58 CMD0(0x11), /* Sleep out */
64 CMD0(0x28), /* Display OFF */
66 CMD0(0x10), /* Sleep in */
97 CMD0(
[all...] |
| /kernel/linux/linux-6.6/drivers/video/backlight/ |
| H A D | tdo24m.c | 41 #define CMD0(x) ((0 << 30) | (x)) macro
48 CMD0(0x1), /* reset */
49 CMD0(0x0), /* nop */
50 CMD0(0x0), /* nop */
51 CMD0(0x0), /* nop */
56 CMD0(0x29), /* Display ON */
58 CMD0(0x11), /* Sleep out */
64 CMD0(0x28), /* Display OFF */
66 CMD0(0x10), /* Sleep in */
97 CMD0(
[all...] |
| /kernel/linux/linux-5.10/drivers/net/ethernet/amd/ |
| H A D | amd8111e.c | 429 writel(RUN, mmio + CMD0); in amd8111e_restart()
490 writel(VAL2 | RDMD0, mmio + CMD0); in amd8111e_restart()
491 writel(VAL0 | INTREN | RUN, mmio + CMD0); in amd8111e_restart()
494 readl(mmio+CMD0); in amd8111e_restart()
507 writel(RUN, mmio + CMD0); in amd8111e_init_hw_default()
521 /* Clear CMD0 */ in amd8111e_init_hw_default()
522 writel(CMD0_CLEAR,mmio + CMD0); in amd8111e_init_hw_default()
595 writel(INTREN, lp->mmio + CMD0); in amd8111e_disable_interrupt()
609 writel(RUN, lp->mmio + CMD0); in amd8111e_stop_chip()
612 readl(lp->mmio + CMD0); in amd8111e_stop_chip()
[all...] |
| H A D | amd8111e.h | 30 Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.
46 #define CMD0 0x48 /* Command0 register */ macro
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/amd/ |
| H A D | amd8111e.c | 428 writel(RUN, mmio + CMD0); in amd8111e_restart()
489 writel(VAL2 | RDMD0, mmio + CMD0); in amd8111e_restart()
490 writel(VAL0 | INTREN | RUN, mmio + CMD0); in amd8111e_restart()
493 readl(mmio+CMD0); in amd8111e_restart()
506 writel(RUN, mmio + CMD0); in amd8111e_init_hw_default()
520 /* Clear CMD0 */ in amd8111e_init_hw_default()
521 writel(CMD0_CLEAR, mmio + CMD0); in amd8111e_init_hw_default()
594 writel(INTREN, lp->mmio + CMD0); in amd8111e_disable_interrupt()
608 writel(RUN, lp->mmio + CMD0); in amd8111e_stop_chip()
611 readl(lp->mmio + CMD0); in amd8111e_stop_chip()
[all...] |
| H A D | amd8111e.h | 30 Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.
46 #define CMD0 0x48 /* Command0 register */ macro
|
Completed in 7 milliseconds