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Searched refs:CM (Results 1 - 11 of 11) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dpp.h34 SRI(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM, id), \
35 SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \
36 SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \
37 SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \
38 SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM, id), \
39 SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM, id), \
40 SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM, id)
43 SRI(CM_BLNDGAM_CONTROL, CM, id), \
44 SRI(CM_BLNDGAM_RAMB_START_CNTL_B, CM, id), \
45 SRI(CM_BLNDGAM_RAMB_START_CNTL_G, CM, i
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dpp.h34 SRI(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM, id), \
35 SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \
36 SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \
37 SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \
38 SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM, id), \
39 SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM, id), \
40 SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM, id)
43 SRI(CM_BLNDGAM_CONTROL, CM, id), \
44 SRI(CM_BLNDGAM_RAMB_START_CNTL_B, CM, id), \
45 SRI(CM_BLNDGAM_RAMB_START_CNTL_G, CM, i
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dpp.h34 SRI(CM_DEALPHA, CM, id),\
35 SRI(CM_MEM_PWR_STATUS, CM, id),\
36 SRI(CM_BIAS_CR_R, CM, id),\
37 SRI(CM_BIAS_Y_G_CB_B, CM, id),\
39 SRI(CM_GAMCOR_CONTROL, CM, id),\
40 SRI(CM_GAMCOR_LUT_CONTROL, CM, id),\
41 SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
42 SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
43 SRI(CM_GAMCOR_LUT_DATA, CM, id),\
44 SRI(CM_GAMCOR_RAMB_START_CNTL_B, CM, i
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dpp.h34 SRI(CM_DEALPHA, CM, id),\
35 SRI(CM_MEM_PWR_STATUS, CM, id),\
36 SRI(CM_BIAS_CR_R, CM, id),\
37 SRI(CM_BIAS_Y_G_CB_B, CM, id),\
39 SRI(CM_GAMCOR_CONTROL, CM, id),\
40 SRI(CM_GAMCOR_LUT_CONTROL, CM, id),\
41 SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
42 SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
43 SRI(CM_GAMCOR_LUT_DATA, CM, id),\
44 SRI(CM_GAMCOR_RAMB_START_CNTL_B, CM, i
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp.h45 SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
46 SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
47 SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
48 SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
49 SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
50 SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
51 SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
78 SRI(CM_ICSC_CONTROL, CM, id), \
79 SRI(CM_ICSC_C11_C12, CM, id), \
80 SRI(CM_ICSC_C33_C34, CM, i
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp.h45 SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
46 SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
47 SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
48 SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
49 SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
50 SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
51 SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
81 SRI(CM_ICSC_CONTROL, CM, id), \
82 SRI(CM_ICSC_C11_C12, CM, id), \
83 SRI(CM_ICSC_C33_C34, CM, i
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource.h431 SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id), \
432 SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id), \
433 SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id), \
434 SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id), \
435 SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \
436 SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \
437 SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id), \
438 SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, i
[all...]
/kernel/linux/linux-5.10/arch/x86/mm/pat/
H A Dmemtype.c191 #define CM(c) (_PAGE_CACHE_MODE_ ## c) macro
199 case PAT_UC: cache = CM(UC); cache_mode = "UC "; break; in pat_get_cache_mode()
200 case PAT_WC: cache = CM(WC); cache_mode = "WC "; break; in pat_get_cache_mode()
201 case PAT_WT: cache = CM(WT); cache_mode = "WT "; break; in pat_get_cache_mode()
202 case PAT_WP: cache = CM(WP); cache_mode = "WP "; break; in pat_get_cache_mode()
203 case PAT_WB: cache = CM(WB); cache_mode = "WB "; break; in pat_get_cache_mode()
204 case PAT_UC_MINUS: cache = CM(UC_MINUS); cache_mode = "UC- "; break; in pat_get_cache_mode()
205 default: cache = CM(WB); cache_mode = "WB "; break; in pat_get_cache_mode()
213 #undef CM macro
/kernel/linux/linux-6.6/arch/x86/mm/pat/
H A Dmemtype.c187 #define CM(c) (_PAGE_CACHE_MODE_ ## c) macro
196 case PAT_UC: cache = CM(UC); cache_mode = "UC "; break; in pat_get_cache_mode()
197 case PAT_WC: cache = CM(WC); cache_mode = "WC "; break; in pat_get_cache_mode()
198 case PAT_WT: cache = CM(WT); cache_mode = "WT "; break; in pat_get_cache_mode()
199 case PAT_WP: cache = CM(WP); cache_mode = "WP "; break; in pat_get_cache_mode()
200 case PAT_WB: cache = CM(WB); cache_mode = "WB "; break; in pat_get_cache_mode()
201 case PAT_UC_MINUS: cache = CM(UC_MINUS); cache_mode = "UC- "; break; in pat_get_cache_mode()
202 default: cache = CM(WB); cache_mode = "WB "; break; in pat_get_cache_mode()
210 #undef CM macro
/kernel/linux/linux-5.10/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c46 #define CM(x) ( \ macro
184 * CM ranges between 16 and 255 in mixel_dphy_config_from_opts()
198 dev_err(&phy->dev, "Invalid CM/CN/CO values: %u/%u/%u\n", in mixel_dphy_config_from_opts()
308 dev_err(&phy->dev, "Invalid CM/CN/CO values! (%u/%u/%u)\n", in mixel_dphy_set_pll_params()
312 dev_dbg(&phy->dev, "Using CM:%u CN:%u CO:%u\n", in mixel_dphy_set_pll_params()
314 phy_write(phy, CM(priv->cfg.cm), DPHY_CM); in mixel_dphy_set_pll_params()
/kernel/linux/linux-6.6/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c62 #define CM(x) ( \ macro
216 * CM ranges between 16 and 255 in mixel_dphy_config_from_opts()
230 dev_err(&phy->dev, "Invalid CM/CN/CO values: %u/%u/%u\n", in mixel_dphy_config_from_opts()
340 dev_err(&phy->dev, "Invalid CM/CN/CO values! (%u/%u/%u)\n", in mixel_dphy_set_pll_params()
344 dev_dbg(&phy->dev, "Using CM:%u CN:%u CO:%u\n", in mixel_dphy_set_pll_params()
346 phy_write(phy, CM(priv->cfg.cm), DPHY_CM); in mixel_dphy_set_pll_params()
430 * CO is configurable, while CN and CM are not, in mixel_dphy_configure_lvds_phy()

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