| /kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 93 #define CLK_TOP_VDEC_SEL 82 macro
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| H A D | mt8173-clk.h | 97 #define CLK_TOP_VDEC_SEL 87 macro
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| H A D | mt2701-clk.h | 93 #define CLK_TOP_VDEC_SEL 82 macro
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| H A D | mt2712-clk.h | 134 #define CLK_TOP_VDEC_SEL 103 macro
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| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 93 #define CLK_TOP_VDEC_SEL 82 macro
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| H A D | mt8173-clk.h | 97 #define CLK_TOP_VDEC_SEL 87 macro
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| H A D | mt2701-clk.h | 93 #define CLK_TOP_VDEC_SEL 82 macro
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| H A D | mt2712-clk.h | 134 #define CLK_TOP_VDEC_SEL 103 macro
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| /kernel/linux/linux-6.6/include/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 95 #define CLK_TOP_VDEC_SEL 84 macro
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| H A D | mt8135-clk.h | 93 #define CLK_TOP_VDEC_SEL 82 macro
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| H A D | mt8173-clk.h | 97 #define CLK_TOP_VDEC_SEL 87 macro
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| H A D | mt2701-clk.h | 93 #define CLK_TOP_VDEC_SEL 82 macro
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| H A D | mt2712-clk.h | 134 #define CLK_TOP_VDEC_SEL 103 macro
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| H A D | mt8192-clk.h | 64 #define CLK_TOP_VDEC_SEL 52 macro
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| /kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 95 #define CLK_TOP_VDEC_SEL 84 macro
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| H A D | mt8135-clk.h | 93 #define CLK_TOP_VDEC_SEL 82 macro
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| H A D | mt8173-clk.h | 97 #define CLK_TOP_VDEC_SEL 87 macro
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| H A D | mt2701-clk.h | 93 #define CLK_TOP_VDEC_SEL 82 macro
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| H A D | mt2712-clk.h | 134 #define CLK_TOP_VDEC_SEL 103 macro
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| H A D | mt8192-clk.h | 64 #define CLK_TOP_VDEC_SEL 52 macro
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| /kernel/linux/linux-6.6/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 461 TOP_MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x50, 8, 4, 15, 0),
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| H A D | clk-mt8173-topckgen.c | 540 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
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| H A D | clk-mt8135.c | 382 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
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| H A D | clk-mt2712.c | 651 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x050, 8, 4, 15),
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| /kernel/linux/linux-5.10/drivers/clk/mediatek/ |
| H A D | clk-mt8135.c | 380 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
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