CLK_BDP_WR_CHANNEL_DI_PXL (reference) in projects: kernel - OpenGrok search results

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Searched refs:CLK_BDP_WR_CHANNEL_DI_PXL (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/mediatek/
H A D	clk-mt2712-bdp.c	`47 GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),`
/kernel/linux/linux-6.6/drivers/clk/mediatek/
H A D	clk-mt2712-bdp.c	`41 GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),`
/kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/
H A D	mt2712-clk.h	`394 #define CLK_BDP_WR_CHANNEL_DI_PXL 16 macro`
/kernel/linux/linux-5.10/include/dt-bindings/clock/
H A D	mt2712-clk.h	`394 #define CLK_BDP_WR_CHANNEL_DI_PXL 16 macro`
/kernel/linux/linux-6.6/include/dt-bindings/clock/
H A D	mt2712-clk.h	`394 #define CLK_BDP_WR_CHANNEL_DI_PXL 16 macro`
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/
H A D	mt2712-clk.h	`394 #define CLK_BDP_WR_CHANNEL_DI_PXL 16 macro`

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