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Searched refs:CLK_BASE__INST3_SEG1 (Results 1 - 22 of 22) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/
H A Dcyan_skillfish_ip_offset.h192 #define CLK_BASE__INST3_SEG1 0 macro
H A Dnavi12_ip_offset.h256 #define CLK_BASE__INST3_SEG1 0x02402400 macro
H A Dnavi14_ip_offset.h256 #define CLK_BASE__INST3_SEG1 0x02402400 macro
H A Dvega20_ip_offset.h232 #define CLK_BASE__INST3_SEG1 0 macro
H A Dnavi10_ip_offset.h205 #define CLK_BASE__INST3_SEG1 0 macro
H A Ddimgrey_cavefish_ip_offset.h238 #define CLK_BASE__INST3_SEG1 0x02402400 macro
H A Dbeige_goby_ip_offset.h267 #define CLK_BASE__INST3_SEG1 0x02402400 macro
H A Dsienna_cichlid_ip_offset.h263 #define CLK_BASE__INST3_SEG1 0x02402400 macro
H A Dyellow_carp_offset.h309 #define CLK_BASE__INST3_SEG1 0x02402400 macro
H A Drenoir_ip_offset.h338 #define CLK_BASE__INST3_SEG1 0 macro
H A Dvega10_ip_offset.h1224 #define CLK_BASE__INST3_SEG1 0 macro
H A Daldebaran_ip_offset.h339 #define CLK_BASE__INST3_SEG1 0x02402400 macro
H A Darct_ip_offset.h324 #define CLK_BASE__INST3_SEG1 0x00017200 macro
H A Dvangogh_ip_offset.h362 #define CLK_BASE__INST3_SEG1 0x02402400 macro
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/
H A Dnavi12_ip_offset.h256 #define CLK_BASE__INST3_SEG1 0x02402400 macro
H A Dnavi14_ip_offset.h256 #define CLK_BASE__INST3_SEG1 0x02402400 macro
H A Dnavi10_ip_offset.h205 #define CLK_BASE__INST3_SEG1 0 macro
H A Dvega20_ip_offset.h232 #define CLK_BASE__INST3_SEG1 0 macro
H A Drenoir_ip_offset.h338 #define CLK_BASE__INST3_SEG1 0 macro
H A Dsienna_cichlid_ip_offset.h263 #define CLK_BASE__INST3_SEG1 0x02402400 macro
H A Dvega10_ip_offset.h1224 #define CLK_BASE__INST3_SEG1 0 macro
H A Darct_ip_offset.h324 #define CLK_BASE__INST3_SEG1 0x00017200 macro

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