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Searched refs:CHL_INT2 (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/scsi/hisi_sas/
H A Dhisi_sas_v1_hw.c173 #define CHL_INT2 (PORT_BASE + 0x1b8) macro
1332 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); in int_phyup_v1_hw()
1392 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, in int_phyup_v1_hw()
1416 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); in int_bcast_v1_hw()
1429 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, in int_bcast_v1_hw()
1715 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT2); in interrupt_openall_v1_hw()
1716 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, val); in interrupt_openall_v1_hw()
H A Dhisi_sas_v3_hw.c274 #define CHL_INT2 (PORT_BASE + 0x1bc) macro
628 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); in init_reg_v3_hw()
985 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk); in disable_phy_v3_hw()
1766 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); in handle_chl_int2_v3_hw()
1825 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); in handle_chl_int2_v3_hw()
2819 HISI_SAS_DEBUGFS_REG(CHL_INT2),
H A Dhisi_sas_v2_hw.c243 #define CHL_INT2 (PORT_BASE + 0x1bc) macro
1253 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff); in init_reg_v2_hw()
2888 CHL_INT2); in int_chnl_int_v2_hw()
2920 CHL_INT2, irq_value2); in int_chnl_int_v2_hw()
/kernel/linux/linux-6.6/drivers/scsi/hisi_sas/
H A Dhisi_sas_v1_hw.c173 #define CHL_INT2 (PORT_BASE + 0x1b8) macro
1327 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); in int_phyup_v1_hw()
1381 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, in int_phyup_v1_hw()
1405 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); in int_bcast_v1_hw()
1417 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, in int_bcast_v1_hw()
1695 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT2); in interrupt_openall_v1_hw()
1696 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, val); in interrupt_openall_v1_hw()
H A Dhisi_sas_v3_hw.c276 #define CHL_INT2 (PORT_BASE + 0x1bc) macro
681 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); in init_reg_v3_hw()
1040 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk); in disable_phy_v3_hw()
1832 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); in handle_chl_int2_v3_hw()
1894 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); in handle_chl_int2_v3_hw()
2973 HISI_SAS_DEBUGFS_REG(CHL_INT2),
H A Dhisi_sas_v2_hw.c243 #define CHL_INT2 (PORT_BASE + 0x1bc) macro
1253 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff); in init_reg_v2_hw()
2883 CHL_INT2); in int_chnl_int_v2_hw()
2915 CHL_INT2, irq_value2); in int_chnl_int_v2_hw()

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