Searched refs:CCSR (Results 1 - 10 of 10) sorted by relevance
| /kernel/linux/linux-5.10/drivers/clk/pxa/ |
| H A D | clk-pxa27x.c | 93 * Get the clock frequency as reflected by CCSR and the turbo flag.
127 unsigned long ccsr = readl(CCSR); in pxa27x_is_ppll_disabled()
229 unsigned long ccsr = readl(CCSR); in clk_pxa27x_cpll_get_rate()
274 unsigned long ccsr = readl(CCSR); in clk_pxa27x_lcd_base_get_rate()
296 unsigned long ccsr = readl(CCSR); in clk_pxa27x_lcd_base_get_parent()
325 unsigned long ccsr = readl(CCSR); in clk_pxa27x_core_get_parent()
362 unsigned long ccsr = readl(CCSR); in clk_pxa27x_run_get_rate()
385 unsigned long ccsr = readl(CCSR); in clk_pxa27x_system_bus_get_rate()
402 unsigned long ccsr = readl(CCSR); in clk_pxa27x_system_bus_get_parent()
419 unsigned long ccsr = readl(CCSR); in clk_pxa27x_memory_get_rate()
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| /kernel/linux/linux-6.6/drivers/clk/pxa/ |
| H A D | clk-pxa27x.c | 71 * Get the clock frequency as reflected by CCSR and the turbo flag.
105 unsigned long ccsr = readl(clk_regs + CCSR); in pxa27x_is_ppll_disabled()
207 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_cpll_get_rate()
252 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_lcd_base_get_rate()
274 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_lcd_base_get_parent()
303 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_core_get_parent()
340 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_run_get_rate()
363 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_system_bus_get_rate()
380 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_system_bus_get_parent()
397 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_memory_get_rate()
[all...] |
| H A D | clk-pxa2xx.h | 6 #define CCSR (0x000C) /* Core Clock Status Register */ macro
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| /kernel/linux/linux-6.6/arch/arm/mach-pxa/ |
| H A D | pxa2xx-regs.h | 135 #define CCSR io_p2v(0x4130000C) /* Core Clock Status Register */ macro
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| /kernel/linux/linux-5.10/arch/arm/mach-pxa/include/mach/ |
| H A D | pxa2xx-regs.h | 135 #define CCSR io_p2v(0x4130000C) /* Core Clock Status Register */ macro
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| /kernel/linux/linux-5.10/drivers/tty/ |
| H A D | synclink.c | 339 #define CCSR 0x04 /* Channel Command/status Register */ macro
2578 * the OnLoop indicator (CCSR:7) should go active in mgsl_txenable()
4849 /* Channel Control/status Register (CCSR) in usc_set_sdlc_mode()
4867 usc_OutReg( info, CCSR, 0x1020 ); in usc_set_sdlc_mode()
5241 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); in usc_process_rxoverrun_sync()
5266 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); in usc_process_rxoverrun_sync()
5296 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT1 in usc_stop_receiver()
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| H A D | clk-imx6sl.c | 17 #define CCSR 0xc macro
128 if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { in imx6sl_get_arm_divider_for_wait()
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| /kernel/linux/linux-6.6/drivers/clk/imx/ |
| H A D | clk-imx6sl.c | 18 #define CCSR 0xc macro
129 if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { in imx6sl_get_arm_divider_for_wait()
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| /kernel/linux/linux-5.10/drivers/net/ethernet/natsemi/ |
| H A D | ns83820.c | 334 #define CCSR 0xcc macro
732 writel(0x0001, dev->base + CCSR); in ns83820_setup_rx()
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| /kernel/linux/linux-6.6/drivers/net/ethernet/natsemi/ |
| H A D | ns83820.c | 334 #define CCSR 0xcc macro
732 writel(0x0001, dev->base + CCSR); in ns83820_setup_rx()
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