/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/include/ |
H A D | rtl8723b_spec.h | 207 #define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ 229 #define IMR_BCNDMAINT7_8723B BIT27 /* Beacon DMA Interrupt 7 */
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H A D | hal_com_reg.h | 777 #define IMR_BCNDMAINT2 BIT27 /* Beacon DMA Interrupt 2 */ 825 #define PHIMR_GTINT3 BIT27 876 #define UHIMR_GTINT3 BIT27 937 #define IMR_GTINT3_88E BIT27 /* When GTIMER3 expires, this bit is set to 1 */ 960 #define IMR_BCNDMAINT7_88E BIT27 /* Beacon DMA Interrupt 7 */ 1024 #define RCR_APP_BA_SSN BIT27 /* SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */ 1586 #define SDIO_HIMR_CTWEND_MSK BIT27 1612 #define SDIO_HISR_CTWEND BIT27
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H A D | osdep_service.h | 48 #define BIT27 0x08000000 macro
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/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/include/ |
H A D | rtl8723b_spec.h | 195 #define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ 217 #define IMR_BCNDMAINT7_8723B BIT27 /* Beacon DMA Interrupt 7 */
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H A D | osdep_service.h | 44 #define BIT27 0x08000000 macro
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H A D | hal_com_reg.h | 688 #define IMR_BCNDMAINT2 BIT27 /* Beacon DMA Interrupt 2 */ 735 #define RCR_APP_BA_SSN BIT27 /* SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */ 1297 #define SDIO_HIMR_CTWEND_MSK BIT27 1319 #define SDIO_HISR_CTWEND BIT27
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/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
H A D | halbt_precomp.h | 58 #define BIT27 0x08000000 macro
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/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
H A D | halbt_precomp.h | 58 #define BIT27 0x08000000 macro
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/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/ |
H A D | Hal8723BReg.h | 389 #define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ 411 #define IMR_BCNDMAINT7_8723B BIT27 /* Beacon DMA Interrupt 7 */
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H A D | rtl8723b_phycfg.c | 810 PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); in phy_PostSetBwMode8723B()
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H A D | HalPhyRf_8723B.c | 746 !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */ in phy_PathA_RxIQK8723B() 1070 !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */ in phy_PathB_RxIQK8723B()
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/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/hal/ |
H A D | Hal8723BReg.h | 384 #define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ 406 #define IMR_BCNDMAINT7_8723B BIT27 /* Beacon DMA Interrupt 7 */
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H A D | rtl8723b_phycfg.c | 657 PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); in phy_PostSetBwMode8723B()
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H A D | HalPhyRf_8723B.c | 642 !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */ in phy_PathA_RxIQK8723B() 922 !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */ in phy_PathB_RxIQK8723B()
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/kernel/linux/linux-5.10/drivers/staging/rtl8192e/ |
H A D | rtl819x_Qos.h | 37 #define BIT27 0x08000000 macro
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/kernel/linux/linux-6.6/drivers/staging/rtl8192e/ |
H A D | rtl819x_Qos.h | 37 #define BIT27 0x08000000 macro
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/kernel/linux/linux-5.10/drivers/staging/rtl8192e/rtl8192e/ |
H A D | r8192E_hw.h | 135 #define RCR_ENMBID BIT27 211 #define IMR_TBDOK BIT27
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/kernel/linux/linux-5.10/include/uapi/linux/ |
H A D | synclink.h | 46 #define BIT27 0x08000000 macro
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/kernel/linux/linux-6.6/drivers/staging/rtl8192e/rtl8192e/ |
H A D | r8192E_hw.h | 105 #define IMR_TBDOK BIT27
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/kernel/linux/linux-6.6/include/uapi/linux/ |
H A D | synclink.h | 46 #define BIT27 0x08000000 macro
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/kernel/linux/patches/linux-6.6/prebuilts/usr/include/linux/ |
H A D | synclink.h | 50 #define BIT27 0x08000000 macro
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/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/ |
H A D | synclink.h | 37 #define BIT27 0x08000000 macro
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/kernel/linux/patches/linux-5.10/prebuilts/usr/include/linux/ |
H A D | synclink.h | 50 #define BIT27 0x08000000 macro
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/kernel/linux/linux-6.6/drivers/scsi/ |
H A D | dc395x.h | 49 #define BIT27 0x08000000 macro
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/kernel/linux/linux-5.10/drivers/scsi/ |
H A D | dc395x.h | 49 #define BIT27 0x08000000 macro
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