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Searched refs:num_states (Results 1 - 25 of 102) sorted by relevance

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/third_party/icu/icu4c/source/i18n/
H A Dregexcst.pl29 $num_states = 1; # Always the state number for the line being compiled.
68 $states{$state_name} = $num_states;
69 $stateNames[$num_states] = $state_name;
90 $state_line_num[$num_states] = $line_num; # remember line number with each state
97 $state_literal_chars[$num_states] = $fields[0];
98 $state_literal_chars[$num_states] =~ s/'//g;
101 $state_char_class[$num_states] = $fields[0];
113 $state_flag[$num_states] = "false";
115 $state_flag[$num_states] = "true";
122 $state_dest_state[$num_states]
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/third_party/node/deps/icu-small/source/i18n/
H A Dregexcst.pl29 $num_states = 1; # Always the state number for the line being compiled.
68 $states{$state_name} = $num_states;
69 $stateNames[$num_states] = $state_name;
90 $state_line_num[$num_states] = $line_num; # remember line number with each state
97 $state_literal_chars[$num_states] = $fields[0];
98 $state_literal_chars[$num_states] =~ s/'//g;
101 $state_char_class[$num_states] = $fields[0];
113 $state_flag[$num_states] = "false";
115 $state_flag[$num_states] = "true";
122 $state_dest_state[$num_states]
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/third_party/skia/third_party/externals/icu/source/i18n/
H A Dregexcst.pl29 $num_states = 1; # Always the state number for the line being compiled.
68 $states{$state_name} = $num_states;
69 $stateNames[$num_states] = $state_name;
90 $state_line_num[$num_states] = $line_num; # remember line number with each state
97 $state_literal_chars[$num_states] = $fields[0];
98 $state_literal_chars[$num_states] =~ s/'//g;
101 $state_char_class[$num_states] = $fields[0];
113 $state_flag[$num_states] = "FALSE";
115 $state_flag[$num_states] = "TRUE";
122 $state_dest_state[$num_states]
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/third_party/icu/icu4c/source/common/
H A Drbbicst.pl30 $num_states = 1; # Always the state number for the line being compiled.
69 $states{$state_name} = $num_states;
70 $stateNames[$num_states] = $state_name;
91 $state_line_num[$num_states] = $line_num; # remember line number with each state
98 $state_literal_chars[$num_states] = $fields[0];
99 $state_literal_chars[$num_states] =~ s/'//g;
102 $state_char_class[$num_states] = $fields[0];
114 $state_flag[$num_states] = "false";
116 $state_flag[$num_states] = "true";
123 $state_dest_state[$num_states]
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/third_party/node/deps/icu-small/source/common/
H A Drbbicst.pl30 $num_states = 1; # Always the state number for the line being compiled.
69 $states{$state_name} = $num_states;
70 $stateNames[$num_states] = $state_name;
91 $state_line_num[$num_states] = $line_num; # remember line number with each state
98 $state_literal_chars[$num_states] = $fields[0];
99 $state_literal_chars[$num_states] =~ s/'//g;
102 $state_char_class[$num_states] = $fields[0];
114 $state_flag[$num_states] = "false";
116 $state_flag[$num_states] = "true";
123 $state_dest_state[$num_states]
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/third_party/skia/third_party/externals/icu/source/common/
H A Drbbicst.pl30 $num_states = 1; # Always the state number for the line being compiled.
69 $states{$state_name} = $num_states;
70 $stateNames[$num_states] = $state_name;
91 $state_line_num[$num_states] = $line_num; # remember line number with each state
98 $state_literal_chars[$num_states] = $fields[0];
99 $state_literal_chars[$num_states] =~ s/'//g;
102 $state_char_class[$num_states] = $fields[0];
114 $state_flag[$num_states] = $javaOutput? "false" : "FALSE";
116 $state_flag[$num_states] = $javaOutput? "true": "TRUE";
123 $state_dest_state[$num_states]
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c125 .num_states = 1,
194 unsigned int num_states = 0; in dcn303_fpu_update_bw_bounding_box() local
276 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
278 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
279 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn303_fpu_update_bw_bounding_box()
282 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box()
283 dram_speed_mts[num_states++] = in dcn303_fpu_update_bw_bounding_box()
291 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
292 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
293 dram_speed_mts[num_states in dcn303_fpu_update_bw_bounding_box()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c126 .num_states = 1,
198 unsigned int num_states = 0; in dcn302_fpu_update_bw_bounding_box() local
282 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
284 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
285 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_fpu_update_bw_bounding_box()
288 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box()
289 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
296 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
297 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
298 dram_speed_mts[num_states in dcn302_fpu_update_bw_bounding_box()
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/kernel/linux/linux-5.10/arch/powerpc/kernel/
H A Drtas-proc.c513 int num_states = 0; in ppc_rtas_process_sensor() local
522 num_states = sizeof(key_switch) / sizeof(char *); in ppc_rtas_process_sensor()
523 if (state < num_states) { in ppc_rtas_process_sensor()
530 num_states = sizeof(enclosure_switch) / sizeof(char *); in ppc_rtas_process_sensor()
531 if (state < num_states) { in ppc_rtas_process_sensor()
543 num_states = sizeof(lid_status) / sizeof(char *); in ppc_rtas_process_sensor()
544 if (state < num_states) { in ppc_rtas_process_sensor()
551 num_states = sizeof(power_source) / sizeof(char *); in ppc_rtas_process_sensor()
552 if (state < num_states) { in ppc_rtas_process_sensor()
563 num_states in ppc_rtas_process_sensor()
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/kernel/linux/linux-6.6/arch/powerpc/kernel/
H A Drtas-proc.c508 int num_states = 0; in ppc_rtas_process_sensor() local
517 num_states = sizeof(key_switch) / sizeof(char *); in ppc_rtas_process_sensor()
518 if (state < num_states) { in ppc_rtas_process_sensor()
525 num_states = sizeof(enclosure_switch) / sizeof(char *); in ppc_rtas_process_sensor()
526 if (state < num_states) { in ppc_rtas_process_sensor()
538 num_states = sizeof(lid_status) / sizeof(char *); in ppc_rtas_process_sensor()
539 if (state < num_states) { in ppc_rtas_process_sensor()
546 num_states = sizeof(power_source) / sizeof(char *); in ppc_rtas_process_sensor()
547 if (state < num_states) { in ppc_rtas_process_sensor()
558 num_states in ppc_rtas_process_sensor()
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/third_party/node/deps/v8/src/compiler/
H A Dnode-marker.cc13 NodeMarkerBase::NodeMarkerBase(Graph* graph, uint32_t num_states) in NodeMarkerBase() argument
14 : mark_min_(graph->mark_max_), mark_max_(graph->mark_max_ += num_states) { in NodeMarkerBase()
15 DCHECK_NE(0u, num_states); // user error! in NodeMarkerBase()
H A Dnode-marker.h21 NodeMarkerBase(Graph* graph, uint32_t num_states);
63 V8_INLINE NodeMarker(Graph* graph, uint32_t num_states) in NodeMarker() argument
64 : NodeMarkerBase(graph, num_states) {} in NodeMarker()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c122 .num_states = 1,
696 unsigned int i = 0, j = 0, num_states = 0; in dcn321_update_bw_bounding_box_fpu() local
767 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
769 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn321_update_bw_bounding_box_fpu()
770 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn321_update_bw_bounding_box_fpu()
773 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn321_update_bw_bounding_box_fpu()
774 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn321_update_bw_bounding_box_fpu()
781 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
782 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn321_update_bw_bounding_box_fpu()
783 dram_speed_mts[num_states in dcn321_update_bw_bounding_box_fpu()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.c212 .num_states = 5,
301 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
343 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { in dcn301_update_bw_bounding_box()
368 dcn3_01_soc.num_states = clk_table->num_entries; in dcn301_update_bw_bounding_box()
370 s[dcn3_01_soc.num_states] = in dcn301_update_bw_bounding_box()
371 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1]; in dcn301_update_bw_bounding_box()
372 s[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states; in dcn301_update_bw_bounding_box()
/kernel/linux/linux-6.6/drivers/regulator/
H A Dirq_helpers.c62 num_rdevs = rid->num_states; in regulator_notifier_isr_work()
167 num_rdevs = rid->num_states; in regulator_notifier_isr()
291 h->rdata.num_states = rdev_amount; in init_rdev_state()
308 for (i = 0; i < h->rdata.num_states; i++) in init_rdev_errors()
427 if (WARN_ON(rid->num_states != 1 || hweight32(err) != 1)) in regulator_irq_map_event_simple()
/third_party/musl/porting/liteos_m/kernel/src/regex/
H A Dregexec.c215 /* Ensure that tbytes and xbytes*num_states cannot overflow, and that in tre_tnfa_run_parallel()
217 if (num_tags > SIZE_MAX/(8 * sizeof(regoff_t) * tnfa->num_states)) in tre_tnfa_run_parallel()
221 if (tnfa->num_states+1 > SIZE_MAX/(8 * sizeof(*reach_next))) in tre_tnfa_run_parallel()
225 if (tnfa->num_states > SIZE_MAX/(8 * sizeof(*reach_pos))) in tre_tnfa_run_parallel()
230 rbytes = sizeof(*reach_next) * (tnfa->num_states + 1); in tre_tnfa_run_parallel()
231 pbytes = sizeof(*reach_pos) * tnfa->num_states; in tre_tnfa_run_parallel()
235 + (rbytes + xbytes * tnfa->num_states) * 2 + tbytes + pbytes; in tre_tnfa_run_parallel()
255 for (i = 0; i < tnfa->num_states; i++) in tre_tnfa_run_parallel()
264 for (i = 0; i < tnfa->num_states; i++) in tre_tnfa_run_parallel()
670 if (tnfa->num_states) in tre_tnfa_run_backtrack()
[all...]
/third_party/musl/porting/liteos_m_iccarm/kernel/src/regex/
H A Dregexec.c215 /* Ensure that tbytes and xbytes*num_states cannot overflow, and that in tre_tnfa_run_parallel()
217 if (num_tags > SIZE_MAX/(8 * sizeof(regoff_t) * tnfa->num_states)) in tre_tnfa_run_parallel()
221 if (tnfa->num_states+1 > SIZE_MAX/(8 * sizeof(*reach_next))) in tre_tnfa_run_parallel()
225 if (tnfa->num_states > SIZE_MAX/(8 * sizeof(*reach_pos))) in tre_tnfa_run_parallel()
230 rbytes = sizeof(*reach_next) * (tnfa->num_states + 1); in tre_tnfa_run_parallel()
231 pbytes = sizeof(*reach_pos) * tnfa->num_states; in tre_tnfa_run_parallel()
235 + (rbytes + xbytes * tnfa->num_states) * 2 + tbytes + pbytes; in tre_tnfa_run_parallel()
255 for (i = 0; i < tnfa->num_states; i++) in tre_tnfa_run_parallel()
264 for (i = 0; i < tnfa->num_states; i++) in tre_tnfa_run_parallel()
670 if (tnfa->num_states) in tre_tnfa_run_backtrack()
[all...]
/third_party/musl/porting/uniproton/kernel/src/regex/
H A Dregexec.c215 /* Ensure that tbytes and xbytes*num_states cannot overflow, and that in tre_tnfa_run_parallel()
217 if (num_tags > SIZE_MAX/(8 * sizeof(regoff_t) * tnfa->num_states)) in tre_tnfa_run_parallel()
221 if (tnfa->num_states+1 > SIZE_MAX/(8 * sizeof(*reach_next))) in tre_tnfa_run_parallel()
225 if (tnfa->num_states > SIZE_MAX/(8 * sizeof(*reach_pos))) in tre_tnfa_run_parallel()
230 rbytes = sizeof(*reach_next) * (tnfa->num_states + 1); in tre_tnfa_run_parallel()
231 pbytes = sizeof(*reach_pos) * tnfa->num_states; in tre_tnfa_run_parallel()
235 + (rbytes + xbytes * tnfa->num_states) * 2 + tbytes + pbytes; in tre_tnfa_run_parallel()
255 for (i = 0; i < tnfa->num_states; i++) in tre_tnfa_run_parallel()
264 for (i = 0; i < tnfa->num_states; i++) in tre_tnfa_run_parallel()
670 if (tnfa->num_states) in tre_tnfa_run_backtrack()
[all...]
/third_party/musl/src/regex/
H A Dregexec.c215 /* Ensure that tbytes and xbytes*num_states cannot overflow, and that in tre_tnfa_run_parallel()
217 if (num_tags > SIZE_MAX/(8 * sizeof(regoff_t) * tnfa->num_states)) in tre_tnfa_run_parallel()
221 if (tnfa->num_states+1 > SIZE_MAX/(8 * sizeof(*reach_next))) in tre_tnfa_run_parallel()
225 if (tnfa->num_states > SIZE_MAX/(8 * sizeof(*reach_pos))) in tre_tnfa_run_parallel()
230 rbytes = sizeof(*reach_next) * (tnfa->num_states + 1); in tre_tnfa_run_parallel()
231 pbytes = sizeof(*reach_pos) * tnfa->num_states; in tre_tnfa_run_parallel()
235 + (rbytes + xbytes * tnfa->num_states) * 2 + tbytes + pbytes; in tre_tnfa_run_parallel()
255 for (i = 0; i < tnfa->num_states; i++) in tre_tnfa_run_parallel()
264 for (i = 0; i < tnfa->num_states; i++) in tre_tnfa_run_parallel()
670 if (tnfa->num_states) in tre_tnfa_run_backtrack()
[all...]
/kernel/linux/linux-5.10/net/netfilter/ipvs/
H A Dip_vs_proto_ah_esp.c119 .num_states = 1,
141 .num_states = 1,
/kernel/linux/linux-6.6/net/netfilter/ipvs/
H A Dip_vs_proto_ah_esp.c119 .num_states = 1,
141 .num_states = 1,
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c169 .num_states = 5,
412 .num_states = 5,
609 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { in dcn31_update_bw_bounding_box()
641 dcn3_1_soc.num_states = clk_table->num_entries; in dcn31_update_bw_bounding_box()
702 dcn3_15_soc.num_states = clk_table->num_entries; in dcn315_update_bw_bounding_box()
748 for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) { in dcn316_update_bw_bounding_box()
758 closest_clk_lvl = dcn3_16_soc.num_states - 1; in dcn316_update_bw_bounding_box()
793 dcn3_16_soc.num_states = clk_table->num_entries; in dcn316_update_bw_bounding_box()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c1669 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1673 (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1686 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1695 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1862 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; in dcn30_internal_validate_bw()
2076 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn30_validate_bandwidth()
2092 unsigned int num_states = 0; in dcn30_update_bw_bounding_box() local
2174 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2176 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2177 dram_speed_mts[num_states in dcn30_update_bw_bounding_box()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c182 .num_states = 1,
1802 dcn3_0_soc.num_states = in init_soc_bounding_box()
1803 le32_to_cpu(bb->num_states); in init_soc_bounding_box()
1805 for (i = 0; i < dcn3_0_soc.num_states; i++) { in init_soc_bounding_box()
1982 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1985 if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1998 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
2021 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
2186 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; in dcn30_internal_validate_bw()
2424 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn30_validate_bandwidth()
2462 unsigned int num_states = 0; dcn30_update_bw_bounding_box() local
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c133 .num_states = 1,
287 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
387 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, in dcn32_predict_pipe_split()
388 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, in dcn32_predict_pipe_split()
428 else if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dppclk_mhz) in dcn32_predict_pipe_split()
1177 if (*vlevel < context->bw_ctx.dml.soc.num_states) { in dcn32_full_validate_bw_helper()
1191 (*vlevel == context->bw_ctx.dml.soc.num_states || in dcn32_full_validate_bw_helper()
1210 /* For the case where *vlevel = num_states, bandwidth validation has failed for this config. in dcn32_full_validate_bw_helper()
1217 if (*vlevel == context->bw_ctx.dml.soc.num_states && in dcn32_full_validate_bw_helper()
1241 for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; in dcn32_full_validate_bw_helper()
2785 unsigned int i = 0, j = 0, num_states = 0; dcn32_update_bw_bounding_box_fpu() local
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