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Searched refs:dst_sel (Results 1 - 25 of 32) sorted by relevance

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/third_party/mesa3d/src/gallium/drivers/r600/sb/
H A Dsb_bc_builder.cpp545 .DST_SEL_X(bc.dst_sel[0]) in build_fetch_tex()
546 .DST_SEL_Y(bc.dst_sel[1]) in build_fetch_tex()
547 .DST_SEL_Z(bc.dst_sel[2]) in build_fetch_tex()
548 .DST_SEL_W(bc.dst_sel[3]) in build_fetch_tex()
596 .DST_SEL_X(bc.dst_sel[0]) in build_fetch_gds()
597 .DST_SEL_Y(bc.dst_sel[1]) in build_fetch_gds()
598 .DST_SEL_Z(bc.dst_sel[2]) in build_fetch_gds()
599 .DST_SEL_W(bc.dst_sel[3]); in build_fetch_gds()
639 .DST_SEL_X(bc.dst_sel[0]) in build_fetch_vtx()
640 .DST_SEL_Y(bc.dst_sel[ in build_fetch_vtx()
[all...]
H A Dsb_bc_decoder.cpp480 bc.dst_sel[0] = w1.get_DST_SEL_X(); in decode_fetch()
481 bc.dst_sel[1] = w1.get_DST_SEL_Y(); in decode_fetch()
482 bc.dst_sel[2] = w1.get_DST_SEL_Z(); in decode_fetch()
483 bc.dst_sel[3] = w1.get_DST_SEL_W(); in decode_fetch()
529 bc.dst_sel[0] = w2.get_DST_SEL_X(); in decode_fetch_gds()
530 bc.dst_sel[1] = w2.get_DST_SEL_Y(); in decode_fetch_gds()
531 bc.dst_sel[2] = w2.get_DST_SEL_Z(); in decode_fetch_gds()
532 bc.dst_sel[3] = w2.get_DST_SEL_W(); in decode_fetch_gds()
562 bc.dst_sel[0] = w1.get_DST_SEL_X(); in decode_fetch_mem()
563 bc.dst_sel[ in decode_fetch_mem()
[all...]
H A Dsb_bc_finalize.cpp494 dst.bc.dst_sel[chan] = SEL_MASK; in copy_fetch_src()
660 unsigned sel = f->bc.dst_sel[chan]; in finalize_fetch()
694 f->bc.dst_sel[i] = dst_swz[i]; in finalize_fetch()
697 f->bc.dst_sel[0] = SEL_MASK; in finalize_fetch()
H A Dsb_bc_dump.cpp493 s << chans[n.bc.dst_sel[k]]; in dump()
H A Dsb_bc.h584 unsigned dst_sel[4]; member
H A Dsb_expr.cpp298 if (n.bc.dst_sel[chan] == SEL_0) in fold()
300 else if (n.bc.dst_sel[chan] == SEL_1) in fold()
H A Dsb_bc_parser.cpp720 if (n->bc.dst_sel[s] != SEL_MASK) in prepare_fetch_clause()
723 // are using, but original n->bc.dst_sel should be taken into in prepare_fetch_clause()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_cp_dma.c448 unsigned size, unsigned dst_sel, unsigned engine, const void *data) in si_cp_write_data()
455 if (sctx->gfx_level == GFX6 && dst_sel == V_370_MEM) in si_cp_write_data()
456 dst_sel = V_370_MEM_GRBM; in si_cp_write_data()
463 radeon_emit(S_370_DST_SEL(dst_sel) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(engine)); in si_cp_write_data()
470 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel, in si_cp_copy_data() argument
487 radeon_emit(COPY_DATA_SRC_SEL(src_sel) | COPY_DATA_DST_SEL(dst_sel) | COPY_DATA_WR_CONFIRM); in si_cp_copy_data()
447 si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset, unsigned size, unsigned dst_sel, unsigned engine, const void *data) si_cp_write_data() argument
H A Dsi_fence.c59 * \param dst_sel MEM or TC_L2
68 unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel, in si_cp_release_mem()
75 unsigned sel = EOP_DST_SEL(dst_sel) | EOP_INT_SEL(int_sel) | EOP_DATA_SEL(data_sel); in si_cp_release_mem()
67 si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigned event, unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel, struct si_resource *buf, uint64_t va, uint32_t new_fence, unsigned query_type) si_cp_release_mem() argument
H A Dsi_pipe.h1453 unsigned size, unsigned dst_sel, unsigned engine, const void *data);
1454 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,
1478 unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel,
/third_party/mesa3d/src/amd/compiler/
H A Daco_validate.cpp172 check(def.bytes() >= sdwa.dst_sel.size() + sdwa.dst_sel.offset(), in validate_ir()
175 sdwa.dst_sel.size() == 1 || sdwa.dst_sel.size() == 2 || sdwa.dst_sel.size() == 4, in validate_ir()
177 check(sdwa.dst_sel.offset() % sdwa.dst_sel.size() == 0, "Invalid selection offset", in validate_ir()
179 check(def.bytes() == 4 || def.bytes() == sdwa.dst_sel.size(), in validate_ir()
180 "SDWA dst_sel size must be definition size for subdword definitions", in validate_ir()
182 check(def.bytes() == 4 || sdwa.dst_sel in validate_ir()
[all...]
H A Daco_opt_value_numbering.cpp197 aSDWA.dst_sel == bSDWA.dst_sel && aSDWA.abs[0] == bSDWA.abs[0] && in operator ()()
H A Daco_print_ir.cpp624 char sext = sdwa.dst_sel.sign_extend() ? 's' : 'u'; in print_instr_format_specific()
625 unsigned offset = sdwa.dst_sel.offset(); in print_instr_format_specific()
628 switch (sdwa.dst_sel.size()) { in print_instr_format_specific()
629 case 1: fprintf(output, " dst_sel:%cbyte%u", sext, offset); break; in print_instr_format_specific()
630 case 2: fprintf(output, " dst_sel:%cword%u", sext, offset >> 1); break; in print_instr_format_specific()
631 case 4: fprintf(output, " dst_sel:dword"); break; in print_instr_format_specific()
H A Daco_assembler.cpp729 encoding |= sdwa.dst_sel.to_sdwa_sel(instr->definitions[0].physReg().byte()) << 8; in emit_instruction()
730 uint32_t dst_u = sdwa.dst_sel.sign_extend() ? 1 : 0; in emit_instruction()
H A Daco_ir.cpp300 sdwa.dst_sel = SubdwordSel(instr->definitions[0].bytes(), 0, false); in convert_to_SDWA()
H A Daco_optimizer.cpp2434 new_sdwa->dst_sel = cmp_sdwa.dst_sel; in combine_inverse_comparison()
3252 if (instr->sdwa().dst_sel.size() != 4) in apply_insert()
3254 static_cast<SDWA_instruction*>(instr.get())->dst_sel = sel; in apply_insert()
3709 if (conv->isSDWA() && (conv->sdwa().dst_sel.size() != 4 || conv->sdwa().sel[0].size() != 2 || in combine_mad_mix()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_pm4_headers_ai.h537 enum mec_release_mem_dst_sel_enum dst_sel:2; member
626 unsigned int dst_sel:4; member
H A Dkfd_pm4_headers_vi.h473 enum RELEASE_MEM_dst_sel_enum dst_sel:2; member
H A Dkfd_packet_manager_v9.c313 packet->bitfields2.dst_sel = dst_sel___write_data__mem_mapped_register; in pm_set_grace_period_v9()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIPeepholeSDWA.cpp18 /// dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
258 << " dst_sel:" << getDstSel() in print()
265 << " dst_sel:" << getDstSel() in print()
399 TII->getNamedImmOperand(MI, AMDGPU::OpName::dst_sel)); in convertToSDWA()
459 // Replace vdst operand in MI with target operand. Set dst_sel and dst_unused in convertToSDWA()
466 // v_mac_f16/32_sdwa allow dst_sel to be equal only to DWORD in convertToSDWA()
475 MachineOperand *DstSel= TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel); in convertToSDWA()
562 // to SDWA dst:v1 dst_sel:WORD_1/BYTE_3 dst_unused:UNUSED_PAD in matchSDWAOperand()
603 // to SDWA dst:v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD in matchSDWAOperand()
717 // v_add_f16_sdwa v0, v1, v2 dst_sel in matchSDWAOperand()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_pm4_headers_diq.h146 enum _RELEASE_MEM_dst_sel_enum dst_sel:2; member
H A Dkfd_pm4_headers_vi.h472 enum RELEASE_MEM_dst_sel_enum dst_sel:2; member
H A Dkfd_pm4_headers_ai.h532 enum mec_release_mem_dst_sel_enum dst_sel:2; member
H A Dkfd_dbgdev.c149 rm_packet->bitfields3.dst_sel = in dbgdev_diq_submit_ib()
/third_party/mesa3d/src/amd/vulkan/
H A Dsi_cmd_buffer.c928 unsigned event, unsigned event_flags, unsigned dst_sel, in si_cs_emit_write_event_eop()
936 unsigned sel = EOP_DST_SEL(dst_sel) | EOP_DATA_SEL(data_sel); in si_cs_emit_write_event_eop()
971 assert(event_flags == 0 && dst_sel == EOP_DST_SEL_MEM && in si_cs_emit_write_event_eop()
927 si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, bool is_mec, unsigned event, unsigned event_flags, unsigned dst_sel, unsigned data_sel, uint64_t va, uint32_t new_fence, uint64_t gfx9_eop_bug_va) si_cs_emit_write_event_eop() argument

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