Home
Sort by
last modified time
|
relevance
|
path
Repository(s)
applications
arkcompiler
base
build
commonlibrary
developtools
device
docs
domains
drivers
foundation
ide
interface
kernel
napi_generator
productdefine
test
third_party
vendor
select all
invert selection
clear
Full Search
Search through all text tokens(words,strings,identifiers,numbers) in index.
Definition
Only finds symbol definitions(where e.g a variable(function,...) is defined).
Symbol
Only finds symbol(e.g. methods classes,function,variables).
File Path
Path of the source file(use "/").If you want just exact path,enclose it in "".Source files end with: .jar/.bz2/.a/.h/.java...
History
History log comments.
Type
Any
Bzip(2)
C
Clojure
C#
C++
ELF
Erlang
Image file
Fortran
Golang
GZIP
Haskell
Jar
Java
Java class
JavaScript
Lisp
Lua
Pascal
Perl
PHP
Plain Text
PL/SQL
Python
Rust
Scala
Shell script
SQL
Tar
Tcl
Troff
UUEncoded
Visual Basic
XML
Zip
Type of analyzer used to filter file types include with selected(e.g. just C sources).
Help
Searched
refs:x300
(Results
1 - 25
of
54
) sorted by relevance
1
2
3
/device/soc/rockchip/rk3588/kernel/drivers/soc/rockchip/
H
A
D
clk.h
66
#define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0
x300
)
104
#define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0
x300
)
127
#define RK1808_SOFTRST_CON(x) ((x) * 0x4 + 0
x300
)
184
#define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0
x300
)
201
#define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0
x300
)
218
#define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0
x300
)
231
#define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0
x300
)
260
#define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0
x300
)
285
#define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0
x300
)
302
#define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0
x300
)
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/
H
A
D
clk.h
66
#define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0
x300
)
104
#define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0
x300
)
127
#define RK1808_SOFTRST_CON(x) ((x) * 0x4 + 0
x300
)
184
#define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0
x300
)
201
#define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0
x300
)
218
#define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0
x300
)
231
#define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0
x300
)
260
#define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0
x300
)
285
#define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0
x300
)
302
#define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0
x300
)
[all...]
/device/soc/hisilicon/common/platform/pin/
H
A
D
pin_hi35xx.h
29
#define PIN_PULL_TYPE_MASK 0
x300
/device/board/hisilicon/hispark_aries/liteos_a/board/include/hisoc/
H
A
D
cpu.h
41
#define ARM_GIC_DIST_ACTIVE_BIT 0
x300
/device/board/hisilicon/hispark_taurus/liteos_a/board/include/hisoc/
H
A
D
cpu.h
41
#define ARM_GIC_DIST_ACTIVE_BIT 0
x300
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/
H
A
D
ddr_ddrt_t12_v100.h
46
#define DDRT_TEST_MODE_MASK 0
x300
/* DDRT Test Mode */
H
A
D
ddr_ddrt_t16.h
46
#define DDRT_TEST_MODE_MASK 0
x300
/* DDRT Test Mode */
H
A
D
ddr_ddrt_t28.h
46
#define DDRT_TEST_MODE_MASK 0
x300
/* DDRT Test Mode */
H
A
D
ddr_ddrt_s40.h
46
#define DDRT_TEST_MODE_MASK 0
x300
/* DDRT Test Mode */
/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/drv/
H
A
D
ddr_ddrt_v2_0_shf1.h
46
#define DDRT_TEST_MODE_MASK 0
x300
/* DDRT Test Mode */
H
A
D
ddr_ddrt_v2_0_shf2.h
46
#define DDRT_TEST_MODE_MASK 0
x300
/* DDRT Test Mode */
H
A
D
ddr_ddrt_v2_0_shf0.h
46
#define DDRT_TEST_MODE_MASK 0
x300
/* DDRT Test Mode */
H
A
D
ddr_ddrt_t12_v100.h
46
#define DDRT_TEST_MODE_MASK 0
x300
/* DDRT Test Mode */
H
A
D
ddr_ddrt_t16.h
46
#define DDRT_TEST_MODE_MASK 0
x300
/* DDRT Test Mode */
H
A
D
ddr_ddrt_s40.h
46
#define DDRT_TEST_MODE_MASK 0
x300
/* DDRT Test Mode */
H
A
D
ddr_ddrt_t28.h
46
#define DDRT_TEST_MODE_MASK 0
x300
/* DDRT Test Mode */
/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H
A
D
clk.h
65
#define PX30_SOFTRST_CON(x) ((x)*0x4 + 0
x300
)
103
#define RV1126_SOFTRST_CON(x) ((x)*0x4 + 0
x300
)
126
#define RK1808_SOFTRST_CON(x) ((x)*0x4 + 0
x300
)
183
#define RK3308_CLKGATE_CON(x) ((x)*0x4 + 0
x300
)
200
#define RK3328_SOFTRST_CON(x) ((x)*0x4 + 0
x300
)
217
#define RK3368_SOFTRST_CON(x) ((x)*0x4 + 0
x300
)
230
#define RK3399_CLKGATE_CON(x) ((x)*0x4 + 0
x300
)
259
#define RK3568_CLKGATE_CON(x) ((x)*0x4 + 0
x300
)
/device/soc/rockchip/rk3399/hardware/mpp/include/
H
A
D
mpp_service.h
80
MPP_CMD_POLL_BASE = 0
x300
,
/device/soc/rockchip/rk3568/hardware/mpp/include/
H
A
D
mpp_service.h
80
MPP_CMD_POLL_BASE = 0
x300
,
/device/soc/rockchip/rk3588/hardware/mpp/include/
H
A
D
mpp_service.h
81
MPP_CMD_POLL_BASE = 0
x300
,
/device/soc/rockchip/common/hardware/mpp/include/
H
A
D
mpp_service.h
80
MPP_CMD_POLL_BASE = 0
x300
,
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H
A
D
aidmp.h
157
uint32 oobaextwidth; /* 0
x300
*/
254
#define OOB_ENABLEC0 0
x300
297
#define AI_OOBAEXTWIDTH 0
x300
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/drivers/core/
H
A
D
drv_symc_v100.h
94
#define REG_MMU_ERR_RDADDR_H_NS 0
x300
/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H
A
D
hi3861_platform_base.h
171
#define GLB_CTL_PAD_SDIO_CFG0_REG (GLB_CTL_BASE + 0
x300
)
298
#define PMU_CMU_CTL_PMU_STATUS_RAW_REG (PMU_CMU_CTL_BASE + 0
x300
)
/device/soc/hisilicon/hi3751v350/sdk_linux/source/common/include/
H
A
D
hi_common.h
62
HI_CHIP_VERSION_V300 = 0
x300
,
Completed in 18 milliseconds
1
2
3