| /device/soc/hisilicon/common/platform/hieth-sf/include/internal/ |
| H A D | eth_phy.h | 32 #define BMCR_SPEED100 0x2000
43 #define BMSR_100HALF 0x2000
56 #define ANLPAR_RF 0x2000
69 #define PHY_1000BTSR_LRS 0x2000
77 #define EXSR_1000TF 0x2000
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| /device/board/hisilicon/hispark_taurus/liteos_a/board/include/asm/ |
| H A D | platform.h | 35 #define GICC_OFFSET 0x2000 /* CPU interface register offset */
54 #define GPIO2_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x2000)
59 #define SPI2_REG_BASE (SPI_REG_ADDR + 0x2000)
69 #define I2C2_REG_PBASE (I2C_REG_ADDR + 0x2000)
85 #define UART2_REG_PBASE (UART_REG_ADDR + 0x2000)
108 #define ETH_REG_OFFSIZE 0x2000
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/include/ |
| H A D | hi3861_platform.h | 24 #define PKT_H_LEN 0x2000 /* PKT_H:8K MIN:7K */
25 #define PKT_B_START_ADDR (0x03100000 + 0x2000 + 0x4000)
31 #define PKT_H_LEN 0x2000 /* PKT_H:8K MIN:7K */
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| H A D | hi_nv.h | 40 #define HI_NV_DEFAULT_TOTAL_SIZE 0x2000
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/common/partition_table/ |
| H A D | load_partition_table.c | 33 #define PRODUCT_CFG_DEFAULT_FNV_SIZE 0x2000 /* 8K */
34 #define PRODUCT_CFG_DEFAULT_NORMAL_NV_SIZE 0x2000 /* 8K */
38 #define PRODUCT_CFG_DEFAULT_HILINK_SIZE 0x2000 /* 8K */
41 #define PRODUCT_CFG_DEFAULT_HILINK_PKI_SIZE 0x2000 /* 8K */
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/common/partition_table/ |
| H A D | boot_partition_table.c | 32 #define PRODUCT_CFG_DEFAULT_FNV_SIZE 0x2000 /* 8K */
33 #define PRODUCT_CFG_DEFAULT_NORMAL_NV_SIZE 0x2000 /* 8K */
37 #define PRODUCT_CFG_DEFAULT_HILINK_SIZE 0x2000 /* 8K */
40 #define PRODUCT_CFG_DEFAULT_HILINK_PKI_SIZE 0x2000 /* 8K */
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| /device/board/hisilicon/hispark_aries/liteos_a/board/include/asm/ |
| H A D | platform.h | 35 #define GICC_OFFSET 0x2000 /* CPU interface register offset */
51 #define ETH_REG_OFFSIZE 0x2000
60 #define GPIO2_REG_BASE (GPIO_REG_BASE + 0x2000)
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/platform/system/partition_table/ |
| H A D | flash_partition_table.c | 39 #define PRODUCT_CFG_DEFAULT_FNV_SIZE 0x2000 /* 8K */
40 #define PRODUCT_CFG_DEFAULT_NORMAL_NV_SIZE 0x2000 /* 8K */
44 #define PRODUCT_CFG_DEFAULT_HILINK_SIZE 0x2000 /* 8K */
47 #define PRODUCT_CFG_DEFAULT_HILINK_PKI_SIZE 0x2000 /* 8K */
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/include/ |
| H A D | hi_nvm.h | 28 #define FACTORY_NV_SIZE 0x2000
105 #define HI_NV_DEFAULT_TOTAL_SIZE 0x2000
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/sys/ |
| H A D | timex.h | 41 #define ADJ_NANO 0x2000
74 #define STA_NANO 0x2000
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| H A D | epoll.h | 31 #define EPOLLRDHUP 0x2000
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| /device/soc/rockchip/rk3568/hardware/omx_il/include/khronos/ |
| H A D | VideoExt.h | 103 OMX_VIDEO_VP9Profile3HDR = 0x2000,
123 OMX_VIDEO_VP9Level62 = 0x2000,
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| /device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/frw/ |
| H A D | frw_main.h | 35 #define FRW_TASK_SIZE 0x2000 /* 驱动task栈大小,默认3k,可初始化配置 */
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| /device/board/hisilicon/hispark_aries/liteos_a/board/include/hisoc/ |
| H A D | cpu.h | 49 #define REG_A7_PERI_GIC_CPU 0x2000
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| /device/board/hisilicon/hispark_taurus/liteos_a/board/include/hisoc/ |
| H A D | cpu.h | 49 #define REG_A7_PERI_GIC_CPU 0x2000
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/ |
| H A D | poll.h | 26 #define POLLRDHUP 0x2000
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| /device/board/hisilicon/hispark_aries/liteos_a/board/ |
| H A D | target_config.h | 79 #define GICC_OFFSET 0x2000 /* CPU interface register offset */
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/common/nvm/ |
| H A D | hi_nvm.h | 27 #define FACTORY_NV_SIZE 0x2000
|
| /device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-samsung-dcphy.c | 1218 regmap_write(samsung->regmap, DPHY_MC_GNR_CON1, T_PHY_READY(0x2000)); in samsung_mipi_dphy_lane_enable()
1225 T_PHY_READY(0x2000)); in samsung_mipi_dphy_lane_enable()
1231 T_PHY_READY(0x2000)); in samsung_mipi_dphy_lane_enable()
1237 T_PHY_READY(0x2000)); in samsung_mipi_dphy_lane_enable()
1244 T_PHY_READY(0x2000)); in samsung_mipi_dphy_lane_enable()
1253 regmap_write(samsung->regmap, COMBO_MD0_GNR_CON1, T_PHY_READY(0x2000)); in samsung_mipi_cphy_lane_enable()
1254 regmap_write(samsung->regmap, COMBO_MD1_GNR_CON1, T_PHY_READY(0x2000)); in samsung_mipi_cphy_lane_enable()
1255 regmap_write(samsung->regmap, COMBO_MD2_GNR_CON1, T_PHY_READY(0x2000)); in samsung_mipi_cphy_lane_enable()
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| /device/board/hisilicon/hispark_taurus/liteos_a/board/ |
| H A D | target_config.h | 86 #define GICC_OFFSET 0x2000 /* CPU interface register offset */
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| /device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/ |
| H A D | sbpcmcia.h | 71 #define F1_MEMOFF 0x2000
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| H A D | sbhnddma.h | 142 #define XS_XS_IDLE 0x2000 /**< idle wait */
182 #define RS_RS_IDLE 0x2000 /**< idle wait */
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/arch/generic/bits/ |
| H A D | ioctl.h | 98 #define TIOCM_OUT1 0x2000
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/net/ |
| H A D | if.h | 163 #define IFF_PORTSEL 0x2000
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| H A D | route.h | 64 #define RTF_THROW 0x2000
|