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/device/soc/hisilicon/hi3516dv300/sdk_linux/usr/sensor/sony_imx458/
H A Dimx458_sensor_ctl.c186 {0x14, 0x4E21},
265 {0x14, 0x942F},
300 {0x14, 0x9483},
301 {0x14, 0x9485},
302 {0x14, 0x9487},
304 {0x14, 0x9503},
305 {0x14, 0x9505},
319 {0x14, 0x9525},
320 {0x14, 0x9527},
321 {0x14,
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/net/ethernet/realtek/r8168/
H A Dr8168_n.c5125 rtl8168_clear_eth_phy_bit(tp, 0x14, BIT_9); in rtl8168_set_speed_xmii()
5128 rtl8168_clear_eth_phy_bit(tp, 0x14, BIT_7); in rtl8168_set_speed_xmii()
6059 rtl8168_set_eth_phy_bit(tp, 0x14, BIT_7); in rtl8168_enable_EEE()
6325 rtl8168_clear_eth_phy_bit(tp, 0x14, BIT_7); in rtl8168_disable_EEE()
6656 rtl8168_set_eth_phy_bit( tp, 0x14, BIT_14 );
6668 rtl8168_mdio_write(tp, 0x14, 0x0000);
6670 rtl8168_mdio_write(tp, 0x14, 0x1222);
6672 rtl8168_mdio_write(tp, 0x14, 0x0022);
6674 rtl8168_set_eth_phy_bit( tp, 0x14, BIT_15 );
6735 rtl8168_clear_eth_phy_bit( tp, 0x14, BIT_1
[all...]
/device/soc/rockchip/common/vendor/drivers/video/rockchip/mpp/hack/
H A Dmpp_rkvdec2_hack_rk3568.c25 0x14, 0xf1, 0x02, 0x36, 0x03, 0x4a, 0x14, 0xf1, 0x02, 0x36, 0x03, 0x4a, 0xe4, 0x7f, 0xe9, 0x68, 0xfa, 0x35, 0xff,
46 0x00, 0x22, 0xff, 0x1e, 0x06, 0x1e, 0x06, 0x20, 0x09, 0x1f, 0x13, 0x1a, 0x1b, 0x1a, 0x1e, 0x25, 0x14, 0x1c, 0x22,
48 0x26, 0x12, 0x2b, 0x14, 0x29, 0x0b, 0x3f, 0x09, 0x3b, 0x09, 0x40, 0xff, 0x5e, 0xfe, 0x59, 0xf7, 0x6c, 0xfa, 0x4c,
63 0x14, 0x1b, 0x00, 0x39, 0xf2, 0x52, 0xfb, 0x4b, 0xed, 0x61, 0xdd, 0x7d, 0x1b, 0x00, 0x1c, 0x00, 0x1f, 0xfc, 0x1b,
65 0x10, 0x41, 0x0e, 0x47, 0x08, 0x3c, 0x06, 0x3f, 0x11, 0x41, 0x15, 0x18, 0x17, 0x14, 0x1a, 0x17, 0x1b, 0x20, 0x1c,
73 0x3c, 0x06, 0x3d, 0x11, 0x37, 0x22, 0x2a, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0xf1, 0x02,
74 0x36, 0x03, 0x4a, 0x14, 0xf1, 0x02, 0x36, 0x03, 0x4a, 0xe4, 0x7f, 0xe9, 0x68, 0xfa, 0x35, 0xff, 0x36, 0x07, 0x33,
87 0xff, 0x37, 0xf9, 0x46, 0xfa, 0x4b, 0xf8, 0x59, 0xde, 0x77, 0xfd, 0x4b, 0x20, 0x14, 0x1e, 0x16, 0xd4, 0x7f, 0x00,
96 0x4b, 0x02, 0x48, 0x08, 0x4d, 0x0e, 0x23, 0x12, 0x1f, 0x11, 0x23, 0x15, 0x1e, 0x11, 0x2d, 0x14,
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/video/rockchip/mpp/hack/
H A Dmpp_rkvdec2_hack_rk3568.c24 0x14, 0xf1, 0x02, 0x36, 0x03, 0x4a, 0x14, 0xf1,
75 0x1f, 0x13, 0x1a, 0x1b, 0x1a, 0x1e, 0x25, 0x14,
79 0x14, 0x29, 0x0b, 0x3f, 0x09, 0x3b, 0x09, 0x40,
114 0x12, 0x1a, 0x14, 0x1b, 0x00, 0x39, 0xf2, 0x52,
120 0x11, 0x41, 0x15, 0x18, 0x17, 0x14, 0x1a, 0x17,
140 0x14, 0xf1, 0x02, 0x36, 0x03, 0x4a, 0x14, 0xf1,
172 0xf8, 0x59, 0xde, 0x77, 0xfd, 0x4b, 0x20, 0x14,
194 0x15, 0x1e, 0x11, 0x2d, 0x14,
[all...]
/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H A Dhi3861_platform_base.h94 #define CLDO_CTL_GEN_REG1 (CLDO_CTL_RB_BASE_ADDR + 0x14) /* used for romboot */
112 #define TIMER_1_BASE_ADDR (TIMER_BASE_ADDR + 0x14)
131 #define RTC_TIMER_1_BASE_ADDR (RTC_TIMER_BASE_ADDR + 0x14)
141 #define GLB_CTL_GP_REG1_REG (GLB_CTL_BASE + 0x14)
352 #define CRG_REG_SC_PERI_CLKEN0_REG (HI_CRG_REG_BASE + 0x14)
394 #define SYSCTRL_SC_PLLCTRL_REG (HI_SYSCTRL_REG_BASE + 0x14)
/device/soc/rockchip/common/vendor/drivers/net/
H A Drfkill-bt.c201 usleep_range(0x0A, 0x14); in rfkill_rk_sleep_bt_internal()
304 msleep(0x14); in rfkill_rk_set_power()
310 msleep(0x14); in rfkill_rk_set_power()
312 msleep(0x14); in rfkill_rk_set_power()
322 msleep(0x14); in rfkill_rk_set_power()
344 msleep(0x14); in rfkill_rk_set_power()
353 msleep(0x14); in rfkill_rk_set_power()
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/cmd_bin/
H A Dcmd_entry_64.S21 stp x13, x14, [sp, #-16]!
61 ldp x13, x14, [sp],#16
/device/soc/rockchip/common/vendor/drivers/input/
H A Drockchip_pwm_remotectl.h18 #define PWM3_REG_INT_EN 0x14 /* Interrupt Enable Refister For Pwm3 */
120 #define PWM_REG_INT_EN(n) ((3 - (n)) * 0x10 + 0x14)
/device/soc/rockchip/rk3588/kernel/drivers/input/remotectl/
H A Drockchip_pwm_remotectl.h19 #define PWM3_REG_INT_EN 0x14 /* Interrupt Enable Refister For Pwm3*/
123 #define PWM_REG_INT_EN(n) ((3 - (n)) * 0x10 + 0x14)
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/drivers/core/
H A Ddrv_symc_v100.h57 #define reg_chann_src_lst_saddr(id) (0x1000 + (id) * 128 + 0x14)
77 #define REG_MMU_INTRAW_S 0x14
H A Ddrv_hash_v100.h30 #define REG_DMA_START_ADDR 0x14
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/scsi/
H A Dscsi.h17 #define RECOVER_BUFFERED_DATA 0x14
81 #define QUEUE_FULL 0x14
/device/soc/hisilicon/common/platform/adc/
H A Dadc_hi35xx.h33 #define HI35XX_ADC_INTR_STATUS 0x14
/device/board/hisilicon/hispark_aries/liteos_a/board/include/hisoc/
H A Dcpu.h32 #define ARM_GIC_CPU_RUNNINGPRI 0x14
H A Dtimer.h33 #define TIMER_MIS 0x14
/device/board/hisilicon/hispark_taurus/liteos_a/board/include/hisoc/
H A Dtimer.h33 #define TIMER_MIS 0x14
H A Dcpu.h32 #define ARM_GIC_CPU_RUNNINGPRI 0x14
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/netinet/
H A Digmp.h22 #define IGMP_PIM 0x14
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/kernel/include/
H A Dlos_sys.h91 #define LOS_ERRNO_SYS_HOOK_IS_FULL LOS_ERRNO_OS_ERROR(LOS_MOD_SYS, 0x14)
/device/soc/rockchip/rk3568/hardware/omx_il/include/khronos/
H A DIVCommonExt.h27 HAL_PIXEL_FORMAT_YCbCr_422_I = 0x14,
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/panel/
H A Dpanel-ilitek-ili9881c.c83 ILI9881C_COMMAND_INSTR(0x12, 0x00), ILI9881C_COMMAND_INSTR(0x13, 0x00), ILI9881C_COMMAND_INSTR(0x14, 0x00),
125 ILI9881C_COMMAND_INSTR(0x60, 0x14), ILI9881C_COMMAND_INSTR(0xA0, 0x2A), ILI9881C_COMMAND_INSTR(0xA1, 0x39),
148 ILI9881C_COMMAND_INSTR(0x12, 0x00), ILI9881C_COMMAND_INSTR(0x13, 0x00), ILI9881C_COMMAND_INSTR(0x14, 0x00),
201 ILI9881C_COMMAND_INSTR(0xA3, 0x14), /* VP243 */
221 ILI9881C_COMMAND_INSTR(0xC3, 0x14), /* VN243 */
297 msleep(0x14); in ili9881c_prepare()
300 msleep(0x14); in ili9881c_prepare()
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/hi_ir/
H A Dhiir.h43 #define IR_IOC_SET_LEADE 0x14
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/commonboot/
H A Dadc_drv.h35 #define REG_ADC_RIS (HI_LS_ADC_REG_BASE + 0x14)
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/startup/
H A Driscv_init_loaderboot.S71 SREG x14, 8 * REGBYTES(sp)
92 LREG x14, 8 * REGBYTES(sp)
118 SREG x14, 14 * REGBYTES(sp)
168 LREG x14, 14 * REGBYTES(sp)
/device/qemu/arm_virt/liteos_a_mini/board/
H A Dtarget_config.h110 #define TIMER_MIS 0x14

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