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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/drivers/core/
H A Ddrv_symc_v100.h51 #define REG_CHAN0_CIPHER_CTRL 0x1000
53 #define reg_chann_ibuf_num(id) (0x1000 + (id) * 128)
54 #define reg_chann_ibuf_cnt(id) (0x1000 + (id) * 128 + 0x4)
55 #define reg_chann_iempty_cnt(id) (0x1000 + (id) * 128 + 0x8)
56 #define reg_chann_cipher_ctrl(id) (0x1000 + (id) * 128 + 0x10)
57 #define reg_chann_src_lst_saddr(id) (0x1000 + (id) * 128 + 0x14)
58 #define reg_chann_iage_cnt(id) (0x1000 + (id) * 128 + 0x1C)
59 #define reg_chann_src_lst_raddr(id) (0x1000 + (id) * 128 + 0x20)
60 #define chnn_src_addr(id) (0x1000 + (id) * 128 + 0x24)
61 #define reg_chann_obuf_num(id) (0x1000
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/device/soc/hisilicon/common/platform/hieth-sf/include/internal/
H A Deth_phy.h33 #define BMCR_AN_ENABLE 0x1000
44 #define BMSR_10FULL 0x1000
70 #define PHY_1000BTSR_RRS 0x1000
78 #define EXSR_1000TH 0x1000
/device/board/hisilicon/hispark_taurus/liteos_a/board/include/asm/
H A Dplatform.h34 #define GICD_OFFSET 0x1000 /* interrupt distributor offset */
55 #define GPIO1_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x1000)
60 #define SPI1_REG_BASE (SPI_REG_ADDR + 0x1000)
70 #define I2C1_REG_PBASE (I2C_REG_ADDR + 0x1000)
86 #define UART1_REG_PBASE (UART_REG_ADDR + 0x1000)
/device/qemu/arm_mps2_an386/liteos_m/board/include/
H A Dsoc.h65 #define GPIO_BASE(no) (0x40010000 + (unsigned int)(no) * 0x1000) /* no: 0 ~ 3 */
66 #define TIMER_BASE(no) (0x40000000 + (unsigned int)(no) * 0x1000)
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/include/
H A Dhi_nvm.h29 #define FLASH_BLOCK_SIZE 0x1000
110 #define HI_NV_DEFAULT_BLOCK_SIZE 0x1000
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/sys/
H A Dtimex.h40 #define ADJ_MICRO 0x1000
73 #define STA_CLOCKERR 0x1000
/device/soc/rockchip/rk3568/hardware/omx_il/include/khronos/
H A DVideoExt.h102 OMX_VIDEO_VP9Profile2HDR = 0x1000,
122 OMX_VIDEO_VP9Level61 = 0x1000,
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hifb/drv/hi3516cv500/
H A Dhifb_def.h31 #define VO_VHD_BASE_ADDR 0x1000 /* V0's base addr */
38 #define VHD_REGS_LEN 0x1000 /* len of V0's regs */
39 #define VSD_REGS_LEN 0x1000
41 #define GFX2_REGS_LEN 0x1000
43 #define DHD_REGS_LEN 0x1000
181 HAL_INPUTFMT_YCBCR_PACKAGE_444 = 0x1000,
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/cbb/vo/vo_dev/arch/hi3516cv500/include/
H A Dvou_def.h30 #define VO_VHD_BASE_ADDR 0x1000 /* V0's base addr */
37 #define VHD_REGS_LEN 0x1000 /* len of V0's regs */
38 #define VSD_REGS_LEN 0x1000
40 #define GFX2_REGS_LEN 0x1000
42 #define DHD_REGS_LEN 0x1000
196 HAL_INPUTFMT_YCBCR_PACKAGE_444 = 0x1000,
/device/soc/rockchip/rk3568/hardware/omx_il/include/librkvpu/
H A Dvpu_api_private_cmd.h24 VPU_API_PRIVATE_HEVC_NEED_PARSE = 0x1000,
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/osal/include/
H A Ddrv_osal_hi3516cv500.h192 .reg_addr_size = 0x1000, \
253 .reg_addr_size = 0x1000, \
/device/board/hisilicon/hispark_aries/liteos_a/board/include/asm/
H A Dplatform.h34 #define GICD_OFFSET 0x1000 /* interrupt distributor offset */
59 #define GPIO1_REG_BASE (GPIO_REG_BASE + 0x1000)
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/osal/linux/mmz/
H A Dcmpi_mm.c74 page_size = ((size + diff - 1) & 0xfffff000UL) + 0x1000; in cmpi_remap_cached()
98 page_size = ((size + diff - 1) & 0xfffff000UL) + 0x1000; in cmpi_remap_nocache()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/lzmaram/
H A Dlzmaram.c23 #define IN_BUF_SIZE 0x1000
24 #define OUT_BUF_SIZE 0x1000
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/common/partition_table/
H A Dload_partition_table.c35 #define PRODUCT_CFG_DEFAULT_NORMAL_NV_BACKUP_SIZE 0x1000 /* 4K */
42 #define PRODUCT_CFG_DEFAULT_CRASH_INFO_SIZE 0x1000 /* 4K */
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/common/partition_table/
H A Dboot_partition_table.c34 #define PRODUCT_CFG_DEFAULT_NORMAL_NV_BACKUP_SIZE 0x1000 /* 4K */
41 #define PRODUCT_CFG_DEFAULT_CRASH_INFO_SIZE 0x1000 /* 4K */
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/system/upg/
H A Dupg_common.h50 #define UPG_FLASH_BLOCK_SIZE 0x1000
51 #define UPG_NV_KERNEL_OFFSET 0x1000
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H A Dbcmnvram.h271 #define ROM_ENVRAM_SPACE 0x1000
282 #define NVRAM_START 0x1000
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_reg.h117 #define GEN8_DRBREGL(x) _MMIO(0x1000 + (x)*8)
119 #define GEN8_DRBREGU(x) _MMIO(0x1000 + (x)*8 + 4)
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/platform/vexpress/
H A Dmali_kbase_cpu_vexpress.c100 syscfg_reg = ioremap(MOTHERBOARD_SYS_CFG_START, 0x1000); in kbase_get_vexpress_cpu_clock_speed()
106 scc_reg = ioremap(CORETILE_EXPRESS_A9X4_SCC_START, 0x1000); in kbase_get_vexpress_cpu_clock_speed()
/device/soc/rockchip/rk2206/hardware/include/lz_hardware/
H A Dthread.h25 #define LZ_HARDWARE_THREAD_STACK_SIZE 0x1000
/device/soc/hisilicon/hi3861v100/sdk_liteos/app/demo/include/
H A Dapp_demo_flash.h30 #define TEST_SIZE 0x1000
/device/soc/hisilicon/hi3861v100/sdk_liteos/third_party/lwip_sack/include/netif/
H A Difaddrs.h73 #define IFF_LINK0 0x1000
199 #define RTF_BLACKHOLE 0x1000
/device/qemu/SmartL_E802/liteos_m/board/fs/
H A Dfs_init.c38 #define FS_INIT_TASK_SIZE 0x1000
/device/qemu/esp32/liteos_m/board/fs/
H A Dfs_init.c38 #define FS_INIT_TASK_SIZE 0x1000

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