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Searched
refs:x1000
(Results
1 - 25
of
175
) sorted by relevance
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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/drivers/core/
H
A
D
drv_symc_v100.h
51
#define REG_CHAN0_CIPHER_CTRL 0
x1000
53
#define reg_chann_ibuf_num(id) (0
x1000
+ (id) * 128)
54
#define reg_chann_ibuf_cnt(id) (0
x1000
+ (id) * 128 + 0x4)
55
#define reg_chann_iempty_cnt(id) (0
x1000
+ (id) * 128 + 0x8)
56
#define reg_chann_cipher_ctrl(id) (0
x1000
+ (id) * 128 + 0x10)
57
#define reg_chann_src_lst_saddr(id) (0
x1000
+ (id) * 128 + 0x14)
58
#define reg_chann_iage_cnt(id) (0
x1000
+ (id) * 128 + 0x1C)
59
#define reg_chann_src_lst_raddr(id) (0
x1000
+ (id) * 128 + 0x20)
60
#define chnn_src_addr(id) (0
x1000
+ (id) * 128 + 0x24)
61
#define reg_chann_obuf_num(id) (0
x1000
[all...]
/device/soc/hisilicon/common/platform/hieth-sf/include/internal/
H
A
D
eth_phy.h
33
#define BMCR_AN_ENABLE 0
x1000
44
#define BMSR_10FULL 0
x1000
70
#define PHY_1000BTSR_RRS 0
x1000
78
#define EXSR_1000TH 0
x1000
/device/board/hisilicon/hispark_taurus/liteos_a/board/include/asm/
H
A
D
platform.h
34
#define GICD_OFFSET 0
x1000
/* interrupt distributor offset */
55
#define GPIO1_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0
x1000
)
60
#define SPI1_REG_BASE (SPI_REG_ADDR + 0
x1000
)
70
#define I2C1_REG_PBASE (I2C_REG_ADDR + 0
x1000
)
86
#define UART1_REG_PBASE (UART_REG_ADDR + 0
x1000
)
/device/qemu/arm_mps2_an386/liteos_m/board/include/
H
A
D
soc.h
65
#define GPIO_BASE(no) (0x40010000 + (unsigned int)(no) * 0
x1000
) /* no: 0 ~ 3 */
66
#define TIMER_BASE(no) (0x40000000 + (unsigned int)(no) * 0
x1000
)
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/include/
H
A
D
hi_nvm.h
29
#define FLASH_BLOCK_SIZE 0
x1000
110
#define HI_NV_DEFAULT_BLOCK_SIZE 0
x1000
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/sys/
H
A
D
timex.h
40
#define ADJ_MICRO 0
x1000
73
#define STA_CLOCKERR 0
x1000
/device/soc/rockchip/rk3568/hardware/omx_il/include/khronos/
H
A
D
VideoExt.h
102
OMX_VIDEO_VP9Profile2HDR = 0
x1000
,
122
OMX_VIDEO_VP9Level61 = 0
x1000
,
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hifb/drv/hi3516cv500/
H
A
D
hifb_def.h
31
#define VO_VHD_BASE_ADDR 0
x1000
/* V0's base addr */
38
#define VHD_REGS_LEN 0
x1000
/* len of V0's regs */
39
#define VSD_REGS_LEN 0
x1000
41
#define GFX2_REGS_LEN 0
x1000
43
#define DHD_REGS_LEN 0
x1000
181
HAL_INPUTFMT_YCBCR_PACKAGE_444 = 0
x1000
,
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/cbb/vo/vo_dev/arch/hi3516cv500/include/
H
A
D
vou_def.h
30
#define VO_VHD_BASE_ADDR 0
x1000
/* V0's base addr */
37
#define VHD_REGS_LEN 0
x1000
/* len of V0's regs */
38
#define VSD_REGS_LEN 0
x1000
40
#define GFX2_REGS_LEN 0
x1000
42
#define DHD_REGS_LEN 0
x1000
196
HAL_INPUTFMT_YCBCR_PACKAGE_444 = 0
x1000
,
/device/soc/rockchip/rk3568/hardware/omx_il/include/librkvpu/
H
A
D
vpu_api_private_cmd.h
24
VPU_API_PRIVATE_HEVC_NEED_PARSE = 0
x1000
,
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/osal/include/
H
A
D
drv_osal_hi3516cv500.h
192
.reg_addr_size = 0
x1000
, \
253
.reg_addr_size = 0
x1000
, \
/device/board/hisilicon/hispark_aries/liteos_a/board/include/asm/
H
A
D
platform.h
34
#define GICD_OFFSET 0
x1000
/* interrupt distributor offset */
59
#define GPIO1_REG_BASE (GPIO_REG_BASE + 0
x1000
)
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/osal/linux/mmz/
H
A
D
cmpi_mm.c
74
page_size = ((size + diff - 1) & 0xfffff000UL) + 0
x1000
;
in cmpi_remap_cached()
98
page_size = ((size + diff - 1) & 0xfffff000UL) + 0
x1000
;
in cmpi_remap_nocache()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/lzmaram/
H
A
D
lzmaram.c
23
#define IN_BUF_SIZE 0
x1000
24
#define OUT_BUF_SIZE 0
x1000
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/common/partition_table/
H
A
D
load_partition_table.c
35
#define PRODUCT_CFG_DEFAULT_NORMAL_NV_BACKUP_SIZE 0
x1000
/* 4K */
42
#define PRODUCT_CFG_DEFAULT_CRASH_INFO_SIZE 0
x1000
/* 4K */
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/common/partition_table/
H
A
D
boot_partition_table.c
34
#define PRODUCT_CFG_DEFAULT_NORMAL_NV_BACKUP_SIZE 0
x1000
/* 4K */
41
#define PRODUCT_CFG_DEFAULT_CRASH_INFO_SIZE 0
x1000
/* 4K */
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/system/upg/
H
A
D
upg_common.h
50
#define UPG_FLASH_BLOCK_SIZE 0
x1000
51
#define UPG_NV_KERNEL_OFFSET 0
x1000
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H
A
D
bcmnvram.h
271
#define ROM_ENVRAM_SPACE 0
x1000
282
#define NVRAM_START 0
x1000
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/i915/gt/uc/
H
A
D
intel_guc_reg.h
117
#define GEN8_DRBREGL(x) _MMIO(0
x1000
+ (x)*8)
119
#define GEN8_DRBREGU(x) _MMIO(0
x1000
+ (x)*8 + 4)
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/platform/vexpress/
H
A
D
mali_kbase_cpu_vexpress.c
100
syscfg_reg = ioremap(MOTHERBOARD_SYS_CFG_START, 0
x1000
);
in kbase_get_vexpress_cpu_clock_speed()
106
scc_reg = ioremap(CORETILE_EXPRESS_A9X4_SCC_START, 0
x1000
);
in kbase_get_vexpress_cpu_clock_speed()
/device/soc/rockchip/rk2206/hardware/include/lz_hardware/
H
A
D
thread.h
25
#define LZ_HARDWARE_THREAD_STACK_SIZE 0
x1000
/device/soc/hisilicon/hi3861v100/sdk_liteos/app/demo/include/
H
A
D
app_demo_flash.h
30
#define TEST_SIZE 0
x1000
/device/soc/hisilicon/hi3861v100/sdk_liteos/third_party/lwip_sack/include/netif/
H
A
D
ifaddrs.h
73
#define IFF_LINK0 0
x1000
199
#define RTF_BLACKHOLE 0
x1000
/device/qemu/SmartL_E802/liteos_m/board/fs/
H
A
D
fs_init.c
38
#define FS_INIT_TASK_SIZE 0
x1000
/device/qemu/esp32/liteos_m/board/fs/
H
A
D
fs_init.c
38
#define FS_INIT_TASK_SIZE 0
x1000
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