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/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/sys/
H A Dmsg.h28 #define MSG_STAT (11 | (IPC_STAT & 0x100))
30 #define MSG_STAT_ANY (13 | (IPC_STAT & 0x100))
H A Dshm.h36 #define SHM_STAT (13 | (IPC_STAT & 0x100))
38 #define SHM_STAT_ANY (15 | (IPC_STAT & 0x100))
H A Dsem.h32 #define SEM_STAT (18 | (IPC_STAT & 0x100))
34 #define SEM_STAT_ANY (20 | (IPC_STAT & 0x100))
H A Dfanotify.h49 #define FAN_CREATE 0x100
71 #define FAN_REPORT_TID 0x100
83 #define FAN_MARK_FILESYSTEM 0x100
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/compat/
H A Dhal_otp.c32 sys_addr = crypto_ioremap_nocache(REG_SYS_OTP_CLK_ADDR_PHY, 0x100); in hal_efuse_otp_init()
50 crypto_iounmap(sys_addr, 0x100); in hal_efuse_otp_init()
52 g_efuse_otp_reg_base = crypto_ioremap_nocache(OTP_REG_BASE_ADDR_PHY, 0x100); in hal_efuse_otp_init()
H A Dhal_efuse.c70 sys_addr = crypto_ioremap_nocache(REG_SYS_EFUSE_CLK_ADDR_PHY, 0x100); // 0x100 for phy addr in hal_efuse_otp_init()
86 crypto_iounmap(sys_addr, 0x100); in hal_efuse_otp_init()
88 g_efuse_otp_reg_base = crypto_ioremap_nocache(ENFUSE_REG_BASE_ADDR_PHY, 0x100); in hal_efuse_otp_init()
/device/board/hisilicon/hispark_aries/liteos_a/board/include/hisoc/
H A Dflash.h85 writel(0x100, IO_MUX_REG_BASE + 0x924); in nand_io_config()
87 writel(0x100, IO_MUX_REG_BASE + 0x92c); in nand_io_config()
88 writel(0x100, IO_MUX_REG_BASE + 0x930); in nand_io_config()
H A Dcpu.h37 #define ARM_GIC_DIST_ENABLE_SET 0x100
/device/board/hisilicon/hispark_taurus/liteos_a/board/include/hisoc/
H A Dflash.h85 writel(0x100, IO_MUX_REG_BASE + 0x924); in nand_io_config()
87 writel(0x100, IO_MUX_REG_BASE + 0x92c); in nand_io_config()
88 writel(0x100, IO_MUX_REG_BASE + 0x930); in nand_io_config()
H A Dcpu.h37 #define ARM_GIC_DIST_ENABLE_SET 0x100
/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/include/linux/mali/
H A Dmali_utgard.h369 .end = (gp_addr) + 0x100, \
383 .end = (gp_addr) + 0x100, \
395 .end = (gp_mmu_addr) + 0x100, \
435 .end = (pp_mmu_addr) + 0x100, \
449 .end = (mmu_addr) + 0x100, \
463 .end = (pmu_addr) + 0x100, \
471 .end = (dma_addr) + 0x100, \
479 .end = (dlbu_addr) + 0x100, \
487 .end = (bcast_addr) + 0x100, \
509 .end = (pp_mmu_bcast_addr) + 0x100, \
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/include/linux/mali/
H A Dmali_utgard.h290 .end = gp_addr + 0x100, \
304 .end = gp_addr + 0x100, \
316 .end = gp_mmu_addr + 0x100, \
356 .end = pp_mmu_addr + 0x100, \
370 .end = mmu_addr + 0x100, \
384 .end = pmu_addr + 0x100, \
392 .end = dma_addr + 0x100, \
400 .end = dlbu_addr + 0x100, \
408 .end = bcast_addr + 0x100, \
430 .end = pp_mmu_bcast_addr + 0x100, \
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk.h61 #define PX30_CLKSEL_CON(x) ((x)*0x4 + 0x100)
96 #define RV1126_PMU_CLKSEL_CON(x) ((x)*0x4 + 0x100)
101 #define RV1126_CLKSEL_CON(x) ((x)*0x4 + 0x100)
124 #define RK1808_CLKSEL_CON(x) ((x)*0x4 + 0x100)
143 #define RK2928_GLB_SRST_FST 0x100
182 #define RK3308_CLKSEL_CON(x) ((x)*0x4 + 0x100)
195 #define RK3328_CLKSEL_CON(x) ((x)*0x4 + 0x100)
197 #define RK3328_GRFCLKSEL_CON(x) ((x)*0x4 + 0x100)
213 #define RK3368_CLKSEL_CON(x) ((x)*0x4 + 0x100)
229 #define RK3399_CLKSEL_CON(x) ((x)*0x4 + 0x100)
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/soc/rockchip/
H A Dclk.h62 #define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
97 #define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
102 #define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
125 #define RK1808_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
144 #define RK2928_GLB_SRST_FST 0x100
183 #define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
196 #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
198 #define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100)
214 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
230 #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/
H A Dclk.h62 #define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
97 #define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
102 #define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
125 #define RK1808_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
144 #define RK2928_GLB_SRST_FST 0x100
183 #define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
196 #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
198 #define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100)
214 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
230 #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
[all...]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/linux/
H A Dmali_kernel_sysfs.c1215 debugfs_create_file("version", 0x100, mali_debugfs_dir, NULL, &version_fops); in mali_sysfs_register()
1237 debugfs_create_file("base_addr", 0x100, mali_gp_gpx_dir, &gp_core->hw_core, in mali_sysfs_register()
1251 debugfs_create_file("num_cores_total", 0x100, mali_pp_dir, NULL, &pp_num_cores_total_fops); in mali_sysfs_register()
1266 debugfs_create_file("base_addr", 0x100, mali_pp_ppx_dir, &pp_core->hw_core, in mali_sysfs_register()
1304 debugfs_create_file("base_addr", 0x100, mali_l2_l2x_dir, &l2_cache->hw_core, in mali_sysfs_register()
1316 debugfs_create_file("utilization_gp_pp", 0x100, mali_debugfs_dir, NULL, &utilization_gp_pp_fops); in mali_sysfs_register()
1317 debugfs_create_file("utilization_gp", 0x100, mali_debugfs_dir, NULL, &utilization_gp_fops); in mali_sysfs_register()
1318 debugfs_create_file("utilization_pp", 0x100, mali_debugfs_dir, NULL, &utilization_pp_fops); in mali_sysfs_register()
1380 debugfs_create_file("events", 0x100, mali_profiling_dir, NULL, &profiling_events_fops); in mali_sysfs_register()
1381 debugfs_create_file("events_human_readable", 0x100, mali_profiling_di in mali_sysfs_register()
[all...]
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H A Dsbsocram.h127 #define SRCI_SRNB_MASK_EXT 0x100
170 #define SOCRAM_BANKIDX_ROM_MASK 0x100
/device/soc/rockchip/rk3588/kernel/include/media/
H A Dv4l2-controls_rockchip.h24 #define RK_V4L2_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_RK_BASE + 0x100)
/device/soc/rockchip/rk3568/hardware/mpp/mpp/legacy/inc/
H A Dmpp_dec_cb_param.h27 DEC_CALLBACK_BASE = 0x100,
/device/board/hisilicon/hispark_taurus/audio_drivers/unittest/src/
H A Dhi3516_aiao_impl_test.c33 int reg = 0x100; in TestAiopRegCfg()
80 const unsigned int offValue = 0x100; in TestAiaoHalReadReg()
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/hi_adc/
H A Dhi_adc.h36 #define LSADC_REG_LENGTH 0x100
/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H A Dhi_os_stat.h39 #define HI_OS_STAT_EVENT_CLR_FAIL 0x100 /**< Invalid input argument.CNcomment:入参错误 CNend */
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/pwm/
H A Dpwm_drv.h24 #define PWM_BASE_ADDR_STEP 0x100
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/
H A Dpoll.h21 #define POLLWRNORM 0x100
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/upg/
H A Dboot_upg_tool.h22 #define HI_BLOCK_SIZE 0x100

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