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/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H A Dspid.h104 #define DATA_UNAVAILABLE 0x0001 /* Requested data not available; Clear by writing a "1" */
138 #define F1_ENABLED 0x0001
143 #define F2_ENABLED 0x0001
148 #define F3_ENABLED 0x0001
H A Dwlioctl_defs.h155 #define WL_STA_CAP_LDPC_CODING 0x0001 /* Support for rx of LDPC coded pkts */
160 #define WL_STA_CAP_MIMO_PS_RTS 0x0001 /* Mimo PS, send RTS/CTS around MIMO frames */
181 #define WL_STA_VHT_LDPCCAP 0x0001
466 #define WSEC_GEN_MIC_ERROR 0x0001
488 #define WEP_ENABLED 0x0001
547 #define WPA_AUTH_NONE 0x0001 /* none (IBSS) */
1648 #define WL_PKT_FILTER_MFLAG_NEG 0x0001
1763 #define LOG_MODULE_COMMON 0x0001
1954 #define IPV4_ARP_FILTER 0x0001
1974 #define TRF_MGMT_FLAG_ADD_DSCP 0x0001 /* Ad
[all...]
H A Dwps.h191 #define WPS_AUTHTYPE_OPEN 0x0001
199 #define WPS_CONFMET_USBA 0x0001 /* Deprecated in WSC 2.0 */
243 #define WPS_DEVICEPWDID_USER_SPEC 0x0001
253 #define WPS_ENCRTYPE_NONE 0x0001
H A Ddhdioctl.h147 #define DHD_ERROR_VAL 0x0001
184 #define DUMP_EAPOL_VAL 0x0001
H A Dpcicfg.h133 #define PCIE_ADVERRREP_CAPID 0x0001
151 #define PCIE_RC_CORR_SERR_EN 0x0001
158 #define PCIE_RC_CRS_VISIBILITY 0x0001
/device/board/hihope/rk3568/audio_drivers/headset_monitor/include/
H A Danalog_headset_base.h22 #define INPUT_DEVID_VENDOR 0x0001
23 #define INPUT_DEVID_PRODUCT 0x0001
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/wtdg/
H A Dwatchdog.h53 #define WDIOF_OVERHEAT 0x0001 /* Reset due to CPU overheat */
65 #define WDIOS_DISABLECARD 0x0001 /* Turn off the watchdog timer */
/device/soc/hisilicon/hi3516dv300/sdk_linux/include/
H A Dwatchdog.h50 #define WDIOF_OVERHEAT 0x0001 /* Reset due to CPU overheat */
62 #define WDIOS_DISABLECARD 0x0001 /* Turn off the watchdog timer */
H A Dhi_resampler_api.h32 #define HI_ERR_RESAMPLE_HANDLE (HI_ERR_RESAMPLE_PREFIX | 0x0001)
/device/soc/hisilicon/hi3516dv300/sdk_liteos/include/
H A Dwatchdog.h48 #define WDIOF_OVERHEAT 0x0001 /* Reset due to CPU overheat */
60 #define WDIOS_DISABLECARD 0x0001 /* Turn off the watchdog timer */
H A Dhi_resampler_api.h32 #define HI_ERR_RESAMPLE_HANDLE (HI_ERR_RESAMPLE_PREFIX | 0x0001)
/device/soc/rockchip/common/vendor/drivers/input/
H A Drockchip_pwm_remotectl.h74 #define PWMDCR_MIN_DUTY 0x0001
77 #define PWMPCR_MIN_PERIOD 0x0001
80 #define PWMPCR_MIN_PERIOD 0x0001
/device/soc/rockchip/rk3588/kernel/drivers/input/remotectl/
H A Drockchip_pwm_remotectl.h75 #define PWMDCR_MIN_DUTY 0x0001
78 #define PWMPCR_MIN_PERIOD 0x0001
81 #define PWMPCR_MIN_PERIOD 0x0001
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/sys/
H A Dtimex.h32 #define ADJ_OFFSET 0x0001
58 #define STA_PLL 0x0001
H A Drandom.h11 #define GRND_NONBLOCK 0x0001
/device/soc/hisilicon/hi3516dv300/sdk_linux/usr/sensor/omnivision_os05a/
H A Dos05a_cmos_ex.h911 { 0x01DF, 0x80D8, 0x8007, 0x8040, 0x01C1, 0x8081, 0x0001, 0x80BF, 0x01BE },
945 { 0x01DF, 0x80D8, 0x8007, 0x8040, 0x01C1, 0x8081, 0x0001, 0x80BF, 0x01BE },
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/netinet/
H A Dip6.h74 #define IP6F_MORE_FRAG 0x0001
129 #define IP6_ALERT_RSVP 0x0001
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/
H A Dstropts.h47 #define S_INPUT 0x0001
62 #define RMSGD 0x0001
/device/qemu/arm_mps3_an547/liteos_m/board/include/
H A Dsoc.h36 #define __CM55_REV 0x0001
/device/soc/hisilicon/hi3516dv300/sdk_linux/usr/sensor/omnivision_os08a10/
H A Dos08a10_cmos_ex.h904 { 0x024C, 0x8134, 0x8018, 0x804B, 0x014A, 0x0001, 0x0010, 0x80F7, 0x01E7 },
938 { 0x024C, 0x8134, 0x8018, 0x804B, 0x014A, 0x0001, 0x0010, 0x80F7, 0x01E7 },
/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/linuxkpi/include/linux/
H A Dpm.h40 #define PM_EVENT_FREEZE 0x0001
/device/qemu/arm_mps2_an386/liteos_m/board/include/
H A Dsoc.h37 #define __CM4_REV 0x0001
/device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/
H A Dphy-rockchip-typec.c450 {0x0001, CMN_DIAG_PLL1_INCLK_CTRL},
460 {0x0001, CMN_DIAG_PLL1_INCLK_CTRL},
469 {0x0008, CMN_DIAG_PLL1_LF_PROG}, {0x0001, CMN_DIAG_PLL1_PTATIS_TUNE1}, {0x0001, CMN_DIAG_PLL1_PTATIS_TUNE2},
470 {0x0001, CMN_DIAG_PLL1_INCLK_CTRL},
479 {0x0008, CMN_DIAG_PLL1_LF_PROG}, {0x0001, CMN_DIAG_PLL1_PTATIS_TUNE1}, {0x0001, CMN_DIAG_PLL1_PTATIS_TUNE2},
480 {0x0001, CMN_DIAG_PLL1_INCLK_CTRL},
489 {0x0008, CMN_DIAG_PLL1_LF_PROG}, {0x0001, CMN_DIAG_PLL1_PTATIS_TUNE1}, {0x0001, CMN_DIAG_PLL1_PTATIS_TUNE
[all...]
/device/soc/rockchip/common/sdk_linux/include/linux/
H A Dreboot.h10 #define SYS_DOWN 0x0001 /* Notify of system down */
/device/soc/rockchip/rk3568/hardware/omx_il/include/rockchip/
H A DRockchip_OMX_Macros.h57 #define ROCKCHIP_TUNNEL_ESTABLISHED 0x0001

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