| /device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/i915/gt/uc/ |
| H A D | intel_guc_fwif.h | 108 u32 header;
109 u32 context_desc;
110 u32 submit_element_info;
111 u32 fence_id;
115 u32 stage_id;
117 u32 head;
118 u32 tail;
119 u32 error_offset;
121 u32 wq_size_bytes;
122 u32 wq_statu
[all...] |
| /device/soc/rockchip/rk3588/kernel/include/linux/ |
| H A D | rockchip-pcie-dma.h | 33 u32 cb :1; // 0
34 u32 tcb :1; // 1
35 u32 llp :1; // 2
36 u32 lie :1; // 3
37 u32 rie :1; // 4
38 u32 cs :2; // 5:6
39 u32 rsvd1 :1; // 7
40 u32 ccs :1; // 8
41 u32 llen :1; // 9
42 u32 b_64
[all...] |
| /device/soc/rockchip/rk3588/kernel/drivers/pci/controller/ |
| H A D | rockchip-pcie-dma.h | 33 u32 cb :1; // 0
34 u32 tcb :1; // 1
35 u32 llp :1; // 2
36 u32 lie :1; // 3
37 u32 rie :1; // 4
38 u32 cs :2; // 5:6
39 u32 rsvd1 :1; // 7
40 u32 ccs :1; // 8
41 u32 llen :1; // 9
42 u32 b_64
[all...] |
| /device/soc/rockchip/common/vendor/drivers/pci/ |
| H A D | rockchip-pcie-dma.h | 30 u32 cb : 1; // 0
31 u32 tcb : 1; // 1
32 u32 llp : 1; // 2
33 u32 lie : 1; // 3
34 u32 rie : 1; // 4
35 u32 cs : 2; // 5:6
36 u32 rsvd1 : 1; // 7
37 u32 ccs : 1; // 8
38 u32 llen : 1; // 9
39 u32 b_64
[all...] |
| /device/soc/rockchip/common/sdk_linux/drivers/pci/controller/ |
| H A D | rockchip-pcie-dma.h | 31 u32 cb : 1; // 0
32 u32 tcb : 1; // 1
33 u32 llp : 1; // 2
34 u32 lie : 1; // 3
35 u32 rie : 1; // 4
36 u32 cs : 2; // 5:6
37 u32 rsvd1 : 1; // 7
38 u32 ccs : 1; // 8
39 u32 llen : 1; // 9
40 u32 b_64
[all...] |
| /device/soc/rockchip/common/sdk_linux/include/linux/rockchip/ |
| H A D | rockchip_sip.h | 117 u32 reserved[20];
118 u32 bank_bit_first;
119 u32 bank_bit_mask;
152 struct arm_smccc_res sip_smc_dram(u32 arg0, u32 arg1, u32 arg2);
153 struct arm_smccc_res sip_smc_request_share_mem(u32 page_num, share_page_type_t page_type);
154 struct arm_smccc_res sip_smc_mcu_el3fiq(u32 arg0, u32 arg1, u32 arg
[all...] |
| /device/soc/rockchip/rk3588/kernel/include/linux/rockchip/ |
| H A D | rockchip_sip.h | 117 u32 reserved[20];
118 u32 bank_bit_first;
119 u32 bank_bit_mask;
152 struct arm_smccc_res sip_smc_dram(u32 arg0, u32 arg1, u32 arg2);
153 struct arm_smccc_res sip_smc_request_share_mem(u32 page_num,
155 struct arm_smccc_res sip_smc_mcu_el3fiq(u32 arg0, u32 arg1, u32 arg
[all...] |
| /device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/ |
| H A D | capture.h | 91 u32 fourcc;
92 u32 mbus_code;
97 u32 write_format;
98 u32 output_format;
142 u32 ctrl;
143 u32 ctrl_shd;
144 u32 scale_hy;
145 u32 scale_hcr;
146 u32 scale_hcb;
147 u32 scale_v
[all...] |
| H A D | isp_params_v3x.h | 29 void (*dpcc_config)(struct rkisp_isp_params_vdev *params_vdev, const struct isp2x_dpcc_cfg *arg, u32 id);
30 void (*dpcc_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id);
31 void (*bls_config)(struct rkisp_isp_params_vdev *params_vdev, const struct isp21_bls_cfg *arg, u32 id);
32 void (*bls_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id);
33 void (*sdg_config)(struct rkisp_isp_params_vdev *params_vdev, const struct isp2x_sdg_cfg *arg, u32 id);
34 void (*sdg_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id);
35 void (*lsc_config)(struct rkisp_isp_params_vdev *params_vdev, const struct isp3x_lsc_cfg *arg, u32 id);
36 void (*lsc_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id);
37 void (*awbgain_config)(struct rkisp_isp_params_vdev *params_vdev, const struct isp21_awb_gain_cfg *arg, u32 id);
38 void (*awbgain_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 i
[all...] |
| /device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/isp/ |
| H A D | capture.h | 91 u32 fourcc;
92 u32 mbus_code;
97 u32 write_format;
98 u32 output_format;
146 u32 ctrl;
147 u32 ctrl_shd;
148 u32 scale_hy;
149 u32 scale_hcr;
150 u32 scale_hcb;
151 u32 scale_v
[all...] |
| H A D | isp_params_v3x.h | 32 const struct isp2x_dpcc_cfg *arg, u32 id);
34 bool en, u32 id);
36 const struct isp21_bls_cfg *arg, u32 id);
38 bool en, u32 id);
40 const struct isp2x_sdg_cfg *arg, u32 id);
42 bool en, u32 id);
44 const struct isp3x_lsc_cfg *arg, u32 id);
46 bool en, u32 id);
48 const struct isp21_awb_gain_cfg *arg, u32 id);
50 bool en, u32 i
[all...] |
| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/csf/ |
| H A D | mali_kbase_csf_firmware.h | 60 #define CSF_HW_DOORBELL_PAGE_OFFSET ((u32)0x80000)
63 #define CSF_HW_DOORBELL_PAGE_SIZE ((u32)0x10000)
66 #define CSF_KERNEL_DOORBELL_NR ((u32)0)
126 u32 features;
138 void kbase_csf_firmware_cs_input(const struct kbase_csf_cmd_stream_info *info, u32 offset, u32 value);
149 u32 kbase_csf_firmware_cs_input_read(const struct kbase_csf_cmd_stream_info *const info, const u32 offset);
160 void kbase_csf_firmware_cs_input_mask(const struct kbase_csf_cmd_stream_info *info, u32 offset, u32 valu
[all...] |
| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/csf/ |
| H A D | mali_kbase_csf_firmware.h | 59 #define CSF_HW_DOORBELL_PAGE_OFFSET ((u32)0x80000)
62 #define CSF_HW_DOORBELL_PAGE_SIZE ((u32)0x10000)
65 #define CSF_KERNEL_DOORBELL_NR ((u32)0)
125 u32 features;
138 const struct kbase_csf_cmd_stream_info *info, u32 offset, u32 value);
148 u32 kbase_csf_firmware_cs_input_read(
149 const struct kbase_csf_cmd_stream_info *const info, const u32 offset);
160 const struct kbase_csf_cmd_stream_info *info, u32 offset,
161 u32 valu
[all...] |
| /device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/include/linux/mali/ |
| H A D | mali_utgard_uk_types.h | 33 u32 points[MALI_UK_TIMELINE_MAX];
152 typedef u32 mali_core_version;
186 u32 cookie; /**< [in] cookie from the mali_uk_gp_job_suspended_s notification */
189 u32 arguments[2]; /**< [in] 0 when aborting a job. When resuming a job, the Mali start and end address for a new
270 u32 priority; /**< [in] job priority. A lower number means higher priority */
271 u32 frame_registers[MALIGP2_NUM_REGS_FRAME]; /**< [in] core specific registers associated with this job */
272 u32 perf_counter_flag; /**< [in] bitmask indicating which performance counters to enable, see \ref
274 u32 perf_counter_src0; /**< [in] source id for performance counter 0 (see ARM DDI0415A, Table 3-60) */
275 u32 perf_counter_src1; /**< [in] source id for performance counter 1 (see ARM DDI0415A, Table 3-60) */
276 u32 frame_builder_i
[all...] |
| /device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/include/linux/mali/ |
| H A D | mali_utgard_uk_types.h | 32 u32 points[MALI_UK_TIMELINE_MAX];
149 typedef u32 _mali_core_version;
184 u32 cookie; /**< [in] cookie from the _mali_uk_gp_job_suspended_s notification */
186 u32 arguments[2]; /**< [in] 0 when aborting a job. When resuming a job, the Mali start and end address for a new heap to resume the job with */
266 u32 priority; /**< [in] job priority. A lower number means higher priority */
267 u32 frame_registers[MALIGP2_NUM_REGS_FRAME]; /**< [in] core specific registers associated with this job */
268 u32 perf_counter_flag; /**< [in] bitmask indicating which performance counters to enable, see \ref _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE and related macro definitions */
269 u32 perf_counter_src0; /**< [in] source id for performance counter 0 (see ARM DDI0415A, Table 3-60) */
270 u32 perf_counter_src1; /**< [in] source id for performance counter 1 (see ARM DDI0415A, Table 3-60) */
271 u32 frame_builder_i
[all...] |
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/hal/phy/hisiv100/regs/ |
| H A D | hdmi_reg_dphy.c | 42 reg_addr = (hi_u32 *)&(g_hdmi2tx_dphy_regs->ssc_in_set.u32); in hdmi_reg_sscin_bypass_en_set()
43 hdmitx_inssc.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_sscin_bypass_en_set()
45 hdmi_tx_reg_write(reg_addr, hdmitx_inssc.u32); in hdmi_reg_sscin_bypass_en_set()
55 reg_addr = (hi_u32 *)&(g_hdmi2tx_dphy_regs->ssc_in_set.u32); in hdmi_reg_pllfbmash111_en_set()
56 hdmitx_inssc.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_pllfbmash111_en_set()
58 hdmi_tx_reg_write(reg_addr, hdmitx_inssc.u32); in hdmi_reg_pllfbmash111_en_set()
68 reg_addr = (hi_u32 *)&(g_hdmi2tx_dphy_regs->dphy_rst.u32); in hdmi_reg_dphy_rst_set()
69 hdmitx_dphy.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_dphy_rst_set()
71 hdmi_tx_reg_write(reg_addr, hdmitx_dphy.u32); in hdmi_reg_dphy_rst_set()
81 reg_addr = (hi_u32 *)&(g_hdmi2tx_dphy_regs->afifo_data_sel.u32); in hdmi_reg_aphy_data_clk_height_set()
[all...] |
| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/ |
| H A D | mali_kbase_gpuprops_types.h | 35 u32 gpu_id;
36 u32 l2_features;
37 u32 l2_config;
38 u32 l2_asn_hash[ASN_HASH_COUNT];
39 u32 core_features;
40 u32 tiler_features;
41 u32 mem_features;
42 u32 mmu_features;
43 u32 as_present;
44 u32 js_presen
[all...] |
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/cbb/vo/vo_dev/arch/hi3516cv500/include/ |
| H A D | vou_reg.h | 43 unsigned int u32; member
74 unsigned int u32; member
105 unsigned int u32; member
136 unsigned int u32; member
160 unsigned int u32; member
191 unsigned int u32; member
222 unsigned int u32; member
253 unsigned int u32; member
279 unsigned int u32; member
300 unsigned int u32; member
321 unsigned int u32; global() member
333 unsigned int u32; global() member
359 unsigned int u32; global() member
373 unsigned int u32; global() member
387 unsigned int u32; global() member
402 unsigned int u32; global() member
414 unsigned int u32; global() member
428 unsigned int u32; global() member
443 unsigned int u32; global() member
455 unsigned int u32; global() member
469 unsigned int u32; global() member
483 unsigned int u32; global() member
497 unsigned int u32; global() member
510 unsigned int u32; global() member
524 unsigned int u32; global() member
536 unsigned int u32; global() member
551 unsigned int u32; global() member
565 unsigned int u32; global() member
597 unsigned int u32; global() member
614 unsigned int u32; global() member
626 unsigned int u32; global() member
668 unsigned int u32; global() member
687 unsigned int u32; global() member
700 unsigned int u32; global() member
713 unsigned int u32; global() member
729 unsigned int u32; global() member
741 unsigned int u32; global() member
753 unsigned int u32; global() member
765 unsigned int u32; global() member
777 unsigned int u32; global() member
789 unsigned int u32; global() member
801 unsigned int u32; global() member
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827 unsigned int u32; global() member
842 unsigned int u32; global() member
854 unsigned int u32; global() member
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882 unsigned int u32; global() member
896 unsigned int u32; global() member
908 unsigned int u32; global() member
920 unsigned int u32; global() member
932 unsigned int u32; global() member
944 unsigned int u32; global() member
956 unsigned int u32; global() member
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980 unsigned int u32; global() member
992 unsigned int u32; global() member
1004 unsigned int u32; global() member
1016 unsigned int u32; global() member
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1864 unsigned int u32; global() member
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1935 unsigned int u32; global() member
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1963 unsigned int u32; global() member
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1987 unsigned int u32; global() member
1999 unsigned int u32; global() member
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5023 unsigned int u32; global() member
5035 unsigned int u32; global() member
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5580 unsigned int u32; global() member
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5750 unsigned int u32; global() member
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5810 unsigned int u32; global() member
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6929 unsigned int u32; global() member
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7260 unsigned int u32; global() member
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8217 unsigned int u32; global() member
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8280 unsigned int u32; global() member
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8320 unsigned int u32; global() member
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8499 unsigned int u32; global() member
8511 unsigned int u32; global() member
8525 unsigned int u32; global() member
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8549 unsigned int u32; global() member
8561 unsigned int u32; global() member
8573 unsigned int u32; global() member
8592 unsigned int u32; global() member
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8616 unsigned int u32; global() member
8628 unsigned int u32; global() member
8640 unsigned int u32; global() member
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8688 unsigned int u32; global() member
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8859 unsigned int u32; global() member
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9094 unsigned int u32; global() member
9108 unsigned int u32; global() member
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[all...] |
| /device/soc/rockchip/common/vendor/drivers/devfreq/ |
| H A D | rockchip_dmc_timing.h | 335 u32 ddr3_speed_bin;
336 u32 pd_idle;
337 u32 sr_idle;
338 u32 auto_pd_dis_freq;
339 u32 auto_sr_dis_freq;
340 u32 ddr3_dll_dis_freq;
341 u32 lpddr2_dll_dis_freq;
342 u32 phy_dll_dis_freq;
343 u32 ddr3_odt_dis_freq;
344 u32 phy_ddr3_odt_disb_fre
[all...] |
| /device/soc/rockchip/rk3588/kernel/drivers/devfreq/ |
| H A D | rockchip_dmc_timing.h | 490 u32 ddr3_speed_bin;
491 u32 pd_idle;
492 u32 sr_idle;
493 u32 auto_pd_dis_freq;
494 u32 auto_sr_dis_freq;
495 u32 ddr3_dll_dis_freq;
496 u32 lpddr2_dll_dis_freq;
497 u32 phy_dll_dis_freq;
498 u32 ddr3_odt_dis_freq;
499 u32 phy_ddr3_odt_disb_fre
[all...] |
| /device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/common/ |
| H A D | mali_osk.h | 268 void _mali_osk_wq_delayed_schedule_work(_mali_osk_wq_delayed_work_t *work, u32 delay);
301 _mali_osk_irq_t *_mali_osk_irq_init(u32 irqnum, _mali_osk_irq_uhandler_t uhandler, void *int_data, _mali_osk_irq_trigger_t trigger_func, _mali_osk_irq_ack_t ack_func, void *probe_data, const char *description);
334 u32 _mali_osk_atomic_dec_return(_mali_osk_atomic_t *atom);
346 u32 _mali_osk_atomic_inc_return(_mali_osk_atomic_t *atom);
350 * @note the parameter required is a u32, and so signed integers should be
351 * cast to u32.
356 void _mali_osk_atomic_init(_mali_osk_atomic_t *atom, u32 val);
366 u32 _mali_osk_atomic_read(_mali_osk_atomic_t *atom);
380 u32 _mali_osk_atomic_xchg(_mali_osk_atomic_t *atom, u32 va
[all...] |
| /device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/common/ |
| H A D | mali_osk.h | 285 void _mali_osk_wq_delayed_schedule_work(_mali_osk_wq_delayed_work_t *work, u32 delay);
317 _mali_osk_irq_t *_mali_osk_irq_init(u32 irqnum, _mali_osk_irq_uhandler_t uhandler, void *int_data,
351 u32 mali_osk_atomic_dec_return(_mali_osk_atomic_t *atom);
363 u32 mali_osk_atomic_inc_return(_mali_osk_atomic_t *atom);
367 * @note the parameter required is a u32, and so signed integers should be
368 * cast to u32.
373 void mali_osk_atomic_init(_mali_osk_atomic_t *atom, u32 val);
383 u32 mali_osk_atomic_read(_mali_osk_atomic_t *atom);
397 u32 mali_osk_atomic_xchg(_mali_osk_atomic_t *atom, u32 va
[all...] |
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/hal/ctrl/hisiv100/regs/ |
| H A D | hdmi_reg_video_path.c | 42 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32); in hdmi_reg_sync_polarity_set()
43 gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_sync_polarity_set()
45 hdmi_tx_reg_write(reg_addr, gen_ctrl.u32); in hdmi_reg_sync_polarity_set()
55 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32); in hdmi_reg_sync_polarity_get()
56 gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_sync_polarity_get()
65 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32); in hdmi_reg_timing_sel_set()
66 gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_timing_sel_set()
68 hdmi_tx_reg_write(reg_addr, gen_ctrl.u32); in hdmi_reg_timing_sel_set()
78 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32); in hdmi_reg_timing_sel_get()
79 gen_ctrl.u32 in hdmi_reg_timing_sel_get()
[all...] |
| H A D | hdmi_reg_audio_path.c | 42 reg_addr = (hi_u32 *)&(g_audio_path_regs->audio_ctl.u32); in hdmi_reg_aud_spdif_en_set()
43 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_aud_spdif_en_set()
45 hdmi_tx_reg_write(reg_addr, ctrl.u32); in hdmi_reg_aud_spdif_en_set()
55 reg_addr = (hi_u32 *)&(g_audio_path_regs->audio_ctl.u32); in hdmi_reg_aud_i2s_en_set()
56 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_aud_i2s_en_set()
58 hdmi_tx_reg_write(reg_addr, ctrl.u32); in hdmi_reg_aud_i2s_en_set()
68 reg_addr = (hi_u32 *)&(g_audio_path_regs->audio_ctl.u32); in hdmi_reg_aud_layout_set()
69 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_aud_layout_set()
71 hdmi_tx_reg_write(reg_addr, ctrl.u32); in hdmi_reg_aud_layout_set()
81 reg_addr = (hi_u32 *)&(g_audio_path_regs->audio_ctl.u32); in hdmi_reg_aud_mute_en_set()
[all...] |
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hifb/drv/hi3516cv500/ |
| H A D | hifb_graphic_hal.c | 47 unsigned int u32; member
212 addr_reg = fb_vou_get_chn_abs_addr(chan, (hi_ulong)(uintptr_t)&(g_hifb_reg->dhd0_ctrl.u32)); in fb_hal_disp_get_intf_enable()
213 dhd0_ctrl.u32 = fb_hal_read_reg((hi_u32 *)(uintptr_t)addr_reg); in fb_hal_disp_get_intf_enable()
237 dhd0_ctrl.u32 = hal_get_addr_chnabs(chan, &(g_hifb_reg->dhd0_ctrl.u32)); in hal_disp_get_intf_sync()
240 dhd0_hsync1.u32 = hal_get_addr_chnabs(chan, &(g_hifb_reg->dhd0_hsync1.u32)); in hal_disp_get_intf_sync()
244 dhd0_hsync2.u32 = hal_get_addr_chnabs(chan, &(g_hifb_reg->dhd0_hsync2.u32)); in hal_disp_get_intf_sync()
249 dhd0_vsync1.u32 in hal_disp_get_intf_sync()
[all...] |