| /device/qemu/drivers/virtio/ |
| H A D | virtblock.c | 79 uint8_t resp; /* and response */ member
137 q->desc[i].pAddr = VMM_TO_DMA_ADDR((VADDR_T)&blk->resp); in PopulateRequestQ()
169 return blk->resp; in VirtblkIO()
271 * resp[0]
272 * resp[1] 1 0
273 * resp[2] 1 1
274 * resp[3]
277 * NOTE: no error check, related 'resp' bits must be zeroed and set only once.
279 static void FillCidCsdBits(uint32_t *resp, int start, int bits, uint32_t value) in FillCidCsdBits() argument
285 resp[inde in FillCidCsdBits()
[all...] |
| H A D | virtgpu.c | 135 struct VirtgpuCtrlHdr resp; member
178 static bool NotifyAndWaitResponse(unsigned queue, struct Virtq *q, const void *req, volatile void *resp) in NotifyAndWaitResponse() argument
181 volatile struct VirtgpuCtrlHdr *b = resp; in NotifyAndWaitResponse()
204 static bool RequestResponse(unsigned queue, const void *req, size_t reqSize, volatile void *resp, size_t respSize) in RequestResponse() argument
215 q->desc[idx].pAddr = VMM_TO_DMA_ADDR((VADDR_T)resp); in RequestResponse()
219 return NotifyAndWaitResponse(queue, q, req, resp); in RequestResponse()
223 size_t dataSize, volatile void *resp, size_t respSize) in RequestDataResponse()
238 q->desc[idx].pAddr = VMM_TO_DMA_ADDR((VADDR_T)resp); in RequestDataResponse()
242 return NotifyAndWaitResponse(0, q, req, resp); in RequestDataResponse()
284 struct VirtgpuRespDisplayInfo resp in CMDGetDisplayInfo() local
222 RequestDataResponse(const void *req, size_t reqSize, const void *data, size_t dataSize, volatile void *resp, size_t respSize) RequestDataResponse() argument
320 struct VirtgpuRespEdid resp = { 0 }; CMDGetEdid() local
346 struct VirtgpuCtrlHdr resp = { 0 }; CMDResourceCreate2D() local
364 struct VirtgpuCtrlHdr resp = { 0 }; CMDSetScanout() local
378 struct VirtgpuCtrlHdr resp = { 0 }; CMDTransferToHost() local
390 struct VirtgpuCtrlHdr resp = { 0 }; CMDResourceFlush() local
416 struct VirtgpuCtrlHdr resp = { 0 }; CMDResourceAttachBacking() local
[all...] |
| /device/qemu/riscv32_virt/liteos_m/board/driver/ |
| H A D | virtgpu.c | 136 struct VirtgpuCtrlHdr resp; member
179 static bool NotifyAndWaitResponse(unsigned queue, struct Virtq *q, const void *req, volatile void *resp) in NotifyAndWaitResponse() argument
182 volatile struct VirtgpuCtrlHdr *b = resp; in NotifyAndWaitResponse()
205 static bool RequestResponse(unsigned queue, const void *req, size_t reqSize, volatile void *resp, size_t respSize) in RequestResponse() argument
216 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)resp)); in RequestResponse()
220 return NotifyAndWaitResponse(queue, q, req, resp); in RequestResponse()
224 size_t dataSize, volatile void *resp, size_t respSize) in RequestDataResponse()
239 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)resp)); in RequestDataResponse()
243 return NotifyAndWaitResponse(0, q, req, resp); in RequestDataResponse()
285 struct VirtgpuRespDisplayInfo resp in CMDGetDisplayInfo() local
223 RequestDataResponse(const void *req, size_t reqSize, const void *data, size_t dataSize, volatile void *resp, size_t respSize) RequestDataResponse() argument
321 struct VirtgpuRespEdid resp = { 0 }; CMDGetEdid() local
347 struct VirtgpuCtrlHdr resp = { 0 }; CMDResourceCreate2D() local
365 struct VirtgpuCtrlHdr resp = { 0 }; CMDSetScanout() local
379 struct VirtgpuCtrlHdr resp = { 0 }; CMDTransferToHost() local
391 struct VirtgpuCtrlHdr resp = { 0 }; CMDResourceFlush() local
419 struct VirtgpuCtrlHdr resp = { 0 }; CMDResourceAttachBacking() local
[all...] |
| /device/soc/rockchip/common/vendor/drivers/mmc/host/ |
| H A D | rk_sdmmc_ops.c | 92 return !(cmd->resp[0] & R1_READY_FOR_DATA) || (R1_CURRENT_STATE(cmd->resp[0]) == 0x07); in rk_emmc_busy()
|
| /device/soc/rockchip/rk3588/kernel/drivers/mmc/host/ |
| H A D | rk_sdmmc_ops.c | 95 return !(cmd->resp[0] & R1_READY_FOR_DATA) || in rk_emmc_busy()
96 (R1_CURRENT_STATE(cmd->resp[0]) == 7); in rk_emmc_busy()
|
| /device/soc/rockchip/common/sdk_linux/drivers/mmc/core/ |
| H A D | block.c | 559 memcpy(&idata->ic.response, cmd.resp, sizeof(cmd.resp));
in mmc_blk_ioctl_cmd_ext()
891 if (!mmc_host_is_spi(card->host) && !(cmd.resp[0] & R1_APP_CMD)) {
in mmc_sd_num_wr_blocks()
1250 val = brq->stop.resp[0] & CMD_ERRORS;
in mmc_blk_eval_resp_error()
1685 (!mmc_host_is_spi(host) && ((mrq->cmd->resp[0] & CMD_ERRORS) || (status & CMD_ERRORS)))) {
in mmc_blk_read_single()
1729 return (brq->cmd.resp[0] & CMD_ERRORS) || (brq->stop.resp[0] & stop_err_bits) || (status & stop_err_bits) ||
in mmc_blk_status_error()
1735 return !brq->sbc.error && !brq->cmd.error && !(brq->cmd.resp[0] & CMD_ERRORS);
in mmc_blk_cmd_started()
1853 return brq->sbc.error || brq->cmd.error || brq->stop.error || brq->data.error || (brq->cmd.resp[0] & CMD_ERRORS);
in mmc_blk_rq_error()
1879 mqrq->brq.cmd.resp[ in mmc_blk_card_busy()
[all...] |
| /device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/ |
| H A D | dhd_msgbuf.c | 4707 DHD_INFO(("%s: Cannot post more than max info resp buffers\n", in dhd_prot_infobufpost()
4923 /* Allocate packet for not ioctl resp buffer post */ in dhd_prot_rxbufpost_ctrl()
5153 DHD_INFO(("ioctl resp buf post\n")); in dhd_msgbuf_rxbuf_post_ioctlresp_bufs()
5156 DHD_INFO(("%s: Cannot post more than max IOCTL resp buffers\n", in dhd_msgbuf_rxbuf_post_ioctlresp_bufs()
6563 info_buf_resp_t *resp; in dhd_prot_process_infobuf_complete() local
6568 resp = (info_buf_resp_t *)buf; in dhd_prot_process_infobuf_complete()
6569 pktid = ltoh32(resp->cmn_hdr.request_id); in dhd_prot_process_infobuf_complete()
6570 buflen = ltoh16(resp->info_data_len); in dhd_prot_process_infobuf_complete()
6578 pktid, buflen, resp->cmn_hdr.flags, ltoh16(resp in dhd_prot_process_infobuf_complete()
9380 h2d_ring_create_response_t *resp = (h2d_ring_create_response_t *)buf; dhd_prot_process_h2d_ring_create_complete() local
9411 d2h_ring_create_response_t *resp = (d2h_ring_create_response_t *)buf; dhd_prot_process_d2h_ring_create_complete() local
[all...] |
| /device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/oal/ |
| H A D | oal_sdio_host.c | 1575 if (cmd.resp[0] & R5_ERROR) { in oal_mmc_io_rw_scat_extended()
1578 if (cmd.resp[0] & R5_FUNCTION_NUMBER) { in oal_mmc_io_rw_scat_extended()
1581 if (cmd.resp[0] & R5_OUT_OF_RANGE) { in oal_mmc_io_rw_scat_extended()
|
| /device/soc/hisilicon/common/platform/mmc/sdhci/ |
| H A D | sdhci.c | 1809 cmd->resp[i] = SdhciReadl(host, RESP01_R + (3 - i) * 4) << 8; in SdhciSaveCommandResp()
1811 cmd->resp[i] |= SdhciReadb(host, RESP01_R + (3 - i) * 4 - 1); in SdhciSaveCommandResp()
1828 cmd->resp[0] = SdhciReadl(host, RESP01_R); in SdhciFinishCommand()
|
| /device/soc/hisilicon/common/platform/mmc/himci_v200/ |
| H A D | himci.c | 480 cmd->resp[0] = HIMCI_READL((uintptr_t)host->base + MMC_RESP0); in HimciCmdDone()
485 cmd->resp[i] = HIMCI_READL((uintptr_t)host->base + MMC_RESP3 - i * 0x4); in HimciCmdDone()
|
| /device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/ |
| H A D | wlioctl.h | 1670 struct dot11_assoc_resp resp; member
5620 uint32 txaddbaresp; /**< addba resp sent */
5632 uint32 rxaddbaresp; /**< addba resp recd */
6440 uint16 response_timeout; /**< ~0 use default, msec to wait for resp after tx packet */
6441 uint16 max_comeback_delay; /**< ~0 use default, max comeback delay in resp else fail */
9473 BSSTRANS_RESP_IMMEDIATE = 4 /**< After an ind, set data and send resp (NOT IMPL) */
11789 wl_nan_instance_id_t peer_instance_id; /* peer instance id of pub/sub req/resp */
12130 /* Return structure to data resp IOVAR */
12477 #define NAN_RNG_TERM_RNG_RESP_REJ 5u /* On range resp, reject from peer */
12478 #define NAN_RNG_TERM_RNG_TXS_FAIL 6u /* On range req/resp tx
[all...] |