Searched refs:reg_value (Results 1 - 9 of 9) sorted by relevance
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/compat/ |
| H A D | hal_otp.c | 64 hi_u32 reg_value = 0; in hal_otp_wait_free() local
67 hal_cipher_read_reg(OTP_USER_CTRL_STA, ®_value); in hal_otp_wait_free()
68 if ((reg_value & 0x1) == 0) { in hal_otp_wait_free()
84 hi_u32 reg_value = otp_mode; in hal_otp_set_mode() local
91 (hi_void)hal_cipher_write_reg(OTP_USER_WORK_MODE, reg_value); in hal_otp_set_mode()
97 hi_u32 reg_value = OTP_OP_START_VAL; in hal_otp_op_start() local
98 (hi_void)hal_cipher_write_reg(OTP_USER_OP_START, reg_value); in hal_otp_op_start()
104 hi_u32 reg_value = 0; in hal_otp_wait_op_done() local
107 hal_cipher_read_reg(OTP_USER_CTRL_STA, ®_value); in hal_otp_wait_op_done()
108 if (reg_value in hal_otp_wait_op_done()
123 hi_u32 reg_value; hal_choose_otp_key() local
[all...] |
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/hal/ctrl/hisiv100/ |
| H A D | hdmi_hal_intf.c | 71 hi_u32 reg_value;
in hal_hdmi_cbar_enable() local
75 reg_value = hdmi_reg_read(reg_addr);
in hal_hdmi_cbar_enable()
78 reg_value |= HDMI_COLOR_BAR_MASK;
in hal_hdmi_cbar_enable()
79 reg_value |= HDMI_COLOR_BAR_UPDATE_MASK;
in hal_hdmi_cbar_enable()
81 reg_value &= ~HDMI_COLOR_BAR_MASK;
in hal_hdmi_cbar_enable()
82 reg_value |= HDMI_COLOR_BAR_UPDATE_MASK;
in hal_hdmi_cbar_enable()
84 hdmi_reg_write(reg_addr, reg_value);
in hal_hdmi_cbar_enable()
|
| H A D | hdmi_hal_ctrl.c | 514 hi_u32 reg_value;
in ctrl_video_color_rgb_set() local
516 reg_value = hdmi_reg_csc_mode_get();
in ctrl_video_color_rgb_set()
519 hdmi_set_bit(reg_value, CTRL_RGB_IN_BIT);
in ctrl_video_color_rgb_set()
521 hdmi_clr_bit(reg_value, CTRL_RGB_IN_BIT);
in ctrl_video_color_rgb_set()
525 hdmi_set_bit(reg_value, CTRL_RGB_OUT_BIT);
in ctrl_video_color_rgb_set()
527 hdmi_clr_bit(reg_value, CTRL_RGB_OUT_BIT);
in ctrl_video_color_rgb_set()
529 hdmi_reg_csc_mode_set(reg_value);
in ctrl_video_color_rgb_set()
822 hi_u32 reg_value;
in ctrl_video_color_rgb_get() local
824 reg_value = hdmi_reg_csc_mode_get();
in ctrl_video_color_rgb_get()
825 *rgb_in = is_bit_set(reg_value, CTRL_RGB_IN_BI in ctrl_video_color_rgb_get()
[all...] |
| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/ |
| H A D | mali_kbase_device.c | 341 u32 reg_value)
in kbase_device_trace_register_access()
373 tb[write_offset * 0x2 + 1] = reg_value;
in kbase_device_trace_register_access()
340 kbase_device_trace_register_access(struct kbase_context *kctx, enum kbase_reg_access_type type, u16 reg_offset, u32 reg_value) kbase_device_trace_register_access() argument
|
| H A D | mali_kbase.h | 197 u32 reg_value);
|
| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/ |
| H A D | mali_kbase_device.c | 331 void kbase_device_trace_register_access(struct kbase_context *kctx, enum kbase_reg_access_type type, u16 reg_offset, u32 reg_value) in kbase_device_trace_register_access() argument
363 tb[write_offset * 2 + 1] = reg_value; in kbase_device_trace_register_access()
|
| H A D | mali_kbase.h | 216 void kbase_device_trace_register_access(struct kbase_context *kctx, enum kbase_reg_access_type type, u16 reg_offset, u32 reg_value);
|
| /device/soc/hisilicon/hi3516dv300/sdk_liteos/include/adapt/ |
| H A D | hi_comm_isp_adapt.h | 2081 hi_u32 reg_value;
member
|
| /device/soc/hisilicon/hi3516dv300/sdk_linux/include/adapt/ |
| H A D | hi_comm_isp_adapt.h | 2081 hi_u32 reg_value;
member
|
Completed in 24 milliseconds