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Searched refs:reg_base (Results 1 - 25 of 62) sorted by relevance

123

/device/soc/rockchip/common/vendor/drivers/devfreq/event/
H A Drockchip-nocp.c39 void __iomem *reg_base; member
49 void __iomem *reg_base = nocp->reg_base; in rockchip_nocp_enable() local
51 writel_relaxed(GLOBAL_EN, reg_base + PROBE_CFGCTL); in rockchip_nocp_enable()
52 writel_relaxed(START_EN, reg_base + PROBE_MAINCTL); in rockchip_nocp_enable()
53 writel_relaxed(0, reg_base + PROBE_STATPERIOD); in rockchip_nocp_enable()
54 writel_relaxed(EVENT_BYTE, reg_base + PROBE_COUNTERS_0_SRC); in rockchip_nocp_enable()
55 writel_relaxed(EVENT_CHAIN, reg_base + PROBE_COUNTERS_1_SRC); in rockchip_nocp_enable()
56 writel_relaxed(START_GO, reg_base + PROBE_STATGO); in rockchip_nocp_enable()
66 void __iomem *reg_base in rockchip_nocp_disable() local
80 void __iomem *reg_base = nocp->reg_base; rockchip_nocp_get_event() local
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/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/spi/
H A Dspi.c27 HI_ALWAYS_STAIC_INLINE hi_bool spi_check_rx_fifo_empty(hi_u32 reg_base) in spi_check_rx_fifo_empty() argument
30 hi_reg_read16(reg_base + REG_SPI_SR, reg_val); in spi_check_rx_fifo_empty()
37 HI_ALWAYS_STAIC_INLINE hi_bool spi_check_busy(hi_u32 reg_base) in spi_check_busy() argument
40 hi_reg_read16(reg_base + REG_SPI_SR, reg_val); in spi_check_busy()
47 HI_ALWAYS_STAIC_INLINE hi_u32 spi_check_write_timeout(hi_u32 reg_base) in spi_check_write_timeout() argument
52 hi_reg_read16(reg_base + REG_SPI_SR, reg_val); in spi_check_write_timeout()
66 HI_ALWAYS_STAIC_INLINE hi_u32 spi_check_tnf_timeout(hi_u32 reg_base, HI_CONST hi_u32 time_out_us) in spi_check_tnf_timeout() argument
71 hi_reg_read16(reg_base + REG_SPI_SR, reg_val); in spi_check_tnf_timeout()
89 HI_ALWAYS_STAIC_INLINE hi_u32 spi_check_rne_timeout(hi_u32 reg_base, HI_CONST hi_u32 time_out_us) in spi_check_rne_timeout() argument
94 hi_reg_read16(reg_base in spi_check_rne_timeout()
110 spi_flush_fifo(hi_u32 reg_base) spi_flush_fifo() argument
276 spi_dma_enable(hi_u32 reg_base, hi_u16 enable_bits) spi_dma_enable() argument
288 spi_dma_disable(hi_u32 reg_base, hi_u16 disable_bits) spi_dma_disable() argument
303 hi_u32 reg_base = spi_dev_ctrl->reg_base; spi_dma_transer() local
432 spi_isr_enable(hi_u32 reg_base, hi_u16 enable_bits) spi_isr_enable() argument
444 spi_isr_disable(hi_u32 reg_base, hi_u16 disable_bits) spi_isr_disable() argument
454 spi_isr_clear_cr(hi_u32 reg_base, hi_u16 clear_bit) spi_isr_clear_cr() argument
469 hi_u32 reg_base = spi_dev_ctrl->reg_base; spi_isr_read_16bits() local
495 hi_u32 reg_base = spi_dev_ctrl->reg_base; spi_isr_read_8bits() local
546 hi_u32 reg_base = spi_dev_ctrl->reg_base; spi_isr_write_fifo() local
582 hi_u32 reg_base = spi_dev_ctrl->reg_base; spi_isr() local
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H A Dspi.h292 hi_u32 reg_base; member
312 hi_void spi_isr_enable(hi_u32 reg_base, hi_u16 enable_bits);
313 hi_void spi_isr_disable(hi_u32 reg_base, hi_u16 disable_bits);
322 hi_void spi_flush_fifo(hi_u32 reg_base);
324 hi_void spi_isr_clear_cr(hi_u32 reg_base, hi_u16 clear_bit);
329 hi_void spi_dma_enable(hi_u32 reg_base, hi_u16 enable_bits);
330 hi_void spi_dma_disable(hi_u32 reg_base, hi_u16 disable_bits);
H A Dhi_spi.c62 spi_isr_enable(g_spi_ctrl[id]->reg_base, SPI_INT_BIT_TX_FIFO_WATER_LINE); in spi_write_data()
84 spi_isr_enable(g_spi_ctrl[id]->reg_base, in spi_read_data()
168 spi_dma_enable(g_spi_ctrl[id]->reg_base, SPI_TX_DMAE); in spi_slave_dma_transfer()
170 spi_dma_disable(g_spi_ctrl[id]->reg_base, SPI_TX_DMAE); in spi_slave_dma_transfer()
172 spi_dma_enable(g_spi_ctrl[id]->reg_base, SPI_RX_DMAE); in spi_slave_dma_transfer()
174 spi_dma_disable(g_spi_ctrl[id]->reg_base, SPI_RX_DMAE); in spi_slave_dma_transfer()
229 spi_flush_fifo(g_spi_ctrl[id]->reg_base); in spi_host_writeread()
258 hi_reg_read16(g_spi_ctrl[id]->reg_base + REG_SPI_CR1, reg_val); in hi_spi_set_loop_back_mode()
260 hi_reg_write16(g_spi_ctrl[id]->reg_base + REG_SPI_CR1, reg_val); in hi_spi_set_loop_back_mode()
333 spi_flush_fifo(g_spi_ctrl[id]->reg_base); in hi_spi_slave_read()
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/device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/
H A Dphy-rockchip-usb.c130 struct regmap *reg_base; member
228 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON3, val); in otg_mode_store()
253 return regmap_write(phy->base->reg_base, phy->reg_offset, val); in rockchip_usb_phy_power()
287 ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val); in rockchip_usb_phy480m_is_enabled()
314 ret = regmap_write(phy->base->reg_base, RK3288_UOC0_CON4, val); in rk3288_usb_phy_init()
450 regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS2, &val); in rk3288_usb_phy_otg_sm_work()
452 regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS2, &val); in rk3288_usb_phy_otg_sm_work()
544 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val); in rk3288_chg_detect_work()
547 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON3, val); in rk3288_chg_detect_work()
550 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON in rk3288_chg_detect_work()
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H A Dphy-rockchip-pcie.c68 struct regmap *reg_base; member
102 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, in phy_wr_cfg()
106 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, in phy_wr_cfg()
109 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, in phy_wr_cfg()
117 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, in phy_rd_cfg()
119 regmap_read(rk_phy->reg_base, rk_phy->phy_data->pcie_status, &val); in phy_rd_cfg()
131 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_laneoff, in rockchip_pcie_phy_power_off()
150 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_laneoff, in rockchip_pcie_phy_power_off()
166 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_laneoff, in rockchip_pcie_phy_power_on()
179 regmap_write(rk_phy->reg_base, rk_ph in rockchip_pcie_phy_power_on()
[all...]
/device/soc/rockchip/common/vendor/drivers/gpio/
H A Dgpio-rockchip.c74 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
85 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
99 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel_bit()
121 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl_bit()
150 data = readl(bank->reg_base + bank->gpio_regs->ext_port); in rockchip_gpio_get()
218 cur_div_reg = readl(bank->reg_base + reg->dbclk_div_con); in rockchip_gpio_set_debounce()
220 writel(div_reg, bank->reg_base + reg->dbclk_div_con); in rockchip_gpio_set_debounce()
325 pend = readl_relaxed(bank->reg_base + reg->int_status); in rockchip_irq_demux()
348 data = readl_relaxed(bank->reg_base + reg->ext_port); in rockchip_irq_demux()
352 polarity = readl_relaxed(bank->reg_base in rockchip_irq_demux()
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/device/soc/rockchip/common/sdk_linux/drivers/gpio/
H A Dgpio-rockchip.c74 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
85 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
99 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel_bit()
121 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl_bit()
150 data = readl(bank->reg_base + bank->gpio_regs->ext_port); in rockchip_gpio_get()
221 cur_div_reg = readl(bank->reg_base + reg->dbclk_div_con); in rockchip_gpio_set_debounce()
223 writel(div_reg, bank->reg_base + reg->dbclk_div_con); in rockchip_gpio_set_debounce()
328 pend = readl_relaxed(bank->reg_base + reg->int_status); in rockchip_irq_demux()
351 data = readl_relaxed(bank->reg_base + reg->ext_port); in rockchip_irq_demux()
355 polarity = readl_relaxed(bank->reg_base in rockchip_irq_demux()
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/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-cpu.c44 * @reg_base: base register for cpu-clock values.
60 void __iomem *reg_base; member
90 u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]); in rockchip_cpuclk_recalc_rate()
114 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_dividers()
164 cpuclk->reg_base + reg_data->core_reg[i]); in rockchip_cpuclk_pre_rate_change()
172 cpuclk->reg_base + reg_data->core_reg[0]); in rockchip_cpuclk_pre_rate_change()
205 cpuclk->reg_base + reg_data->core_reg[0]); in rockchip_cpuclk_post_rate_change()
210 cpuclk->reg_base + reg_data->core_reg[i]); in rockchip_cpuclk_post_rate_change()
248 void __iomem *reg_base, spinlock_t *lock) in rockchip_clk_register_cpuclk()
285 cpuclk->reg_base in rockchip_clk_register_cpuclk()
245 rockchip_clk_register_cpuclk(const char *name, u8 num_parents, struct clk *parent, struct clk *alt_parent, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, int nrates, void __iomem *reg_base, spinlock_t *lock) rockchip_clk_register_cpuclk() argument
[all...]
H A Dclk-pll.c39 void __iomem *reg_base; member
417 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1), pllcon, pllcon & RK3036_PLLCON1_LOCK_STATUS, 0, in rockchip_rk3036_pll_wait_lock()
448 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0)); in rockchip_rk3036_pll_get_params()
452 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_get_params()
457 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); in rockchip_rk3036_pll_get_params()
515 pll->reg_base + RK3036_PLLCON(0)); in rockchip_rk3036_pll_set_params()
520 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_set_params()
523 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0x2)); in rockchip_rk3036_pll_set_params()
526 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(0x2)); in rockchip_rk3036_pll_set_params()
565 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), pll->reg_base in rockchip_rk3036_pll_enable()
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H A Dclk.c434 ctx->reg_base = base; in rockchip_clk_init()
503 ctx->reg_base + list->muxdiv_offset, list->mux_shift, in rockchip_clk_register_branches()
507 ctx->reg_base + list->muxdiv_offset, list->mux_shift, list->mux_width, in rockchip_clk_register_branches()
524 ctx->reg_base + list->muxdiv_offset, list->div_shift, in rockchip_clk_register_branches()
528 ctx->reg_base + list->muxdiv_offset, list->div_shift, list->div_width, in rockchip_clk_register_branches()
534 ctx->reg_base, list->muxdiv_offset, list->div_flags, in rockchip_clk_register_branches()
539 clk = rockchip_clk_register_halfdiv(list->name, list->parent_names, list->num_parents, ctx->reg_base, in rockchip_clk_register_branches()
549 clk_register_gate(NULL, list->name, list->parent_names[0], flags, ctx->reg_base + list->gate_offset, in rockchip_clk_register_branches()
553 clk = rockchip_clk_register_branch(list->name, list->parent_names, list->num_parents, ctx->reg_base, in rockchip_clk_register_branches()
561 ctx, list->name, list->parent_names, list->num_parents, ctx->reg_base, lis in rockchip_clk_register_branches()
[all...]
H A Dclk-ddr.c28 void __iomem *reg_base; member
99 val = readl(ddrclk->reg_base + ddrclk->mux_offset) >> ddrclk->mux_shift; in rockchip_ddrclk_get_parent()
220 int ddr_flag, void __iomem *reg_base) in rockchip_clk_register_ddrclk()
260 ddrclk->reg_base = reg_base; in rockchip_clk_register_ddrclk()
218 rockchip_clk_register_ddrclk(const char *name, int flags, const char *const *parent_names, u8 num_parents, int mux_offset, int mux_shift, int mux_width, int div_shift, int div_width, int ddr_flag, void __iomem *reg_base) rockchip_clk_register_ddrclk() argument
H A Dclk-rk3036.c385 void __iomem *reg_base; in rk3036_clk_init() local
389 reg_base = of_iomap(np, 0); in rk3036_clk_init()
390 if (!reg_base) { in rk3036_clk_init()
399 writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 0xa), reg_base + RK2928_CLKSEL_CON(0xd)); in rk3036_clk_init()
401 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); in rk3036_clk_init()
404 iounmap(reg_base); in rk3036_clk_init()
420 rockchip_register_softrst(np, 0x9, reg_base + RK2928_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK); in rk3036_clk_init()
427 rk3036_cru_base = reg_base; in rk3036_clk_init()
H A Dclk-rk3128.c488 void __iomem *reg_base; in rk3128_common_clk_init() local
491 reg_base = of_iomap(np, 0); in rk3128_common_clk_init()
492 if (!reg_base) { in rk3128_common_clk_init()
497 rk312x_reg_base = reg_base; in rk3128_common_clk_init()
498 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); in rk3128_common_clk_init()
501 iounmap(reg_base); in rk3128_common_clk_init()
512 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK); in rk3128_common_clk_init()
/device/soc/rockchip/rk3588/kernel/drivers/gpio/
H A Dgpio-rockchip.c77 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
88 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
103 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel_bit()
124 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl_bit()
181 data = readl(bank->reg_base + bank->gpio_regs->ext_port); in rockchip_gpio_get()
218 cur_div_reg = readl(bank->reg_base + in rockchip_gpio_set_debounce()
221 writel(div_reg, bank->reg_base + in rockchip_gpio_set_debounce()
339 pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status); in rockchip_irq_demux()
363 data = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
368 polarity = readl_relaxed(bank->reg_base in rockchip_irq_demux()
[all...]
/device/soc/rockchip/common/vendor/drivers/video/rockchip/mpp/
H A Dmpp_rkvdec2_link.c118 void __iomem *reg_base = dev->reg_base; in rkvdec_link_status_update() local
123 error_ff1 = (readl(reg_base + RKVDEC_LINK_DEC_NUM_BASE) & RKVDEC_LINK_BIT_DEC_ERROR) ? 1 : 0; in rkvdec_link_status_update()
124 enable_ff1 = readl(reg_base + RKVDEC_LINK_EN_BASE); in rkvdec_link_status_update()
125 dev->irq_status = readl(reg_base + RKVDEC_LINK_IRQ_BASE); in rkvdec_link_status_update()
126 dev->iova_curr = readl(reg_base + RKVDEC_LINK_CFG_ADDR_BASE); in rkvdec_link_status_update()
127 dev->link_mode = readl(reg_base + RKVDEC_LINK_MODE_BASE); in rkvdec_link_status_update()
128 dev->total = readl(reg_base + RKVDEC_LINK_TOTAL_NUM_BASE); in rkvdec_link_status_update()
129 dev->iova_next = readl(reg_base + RKVDEC_LINK_NEXT_ADDR_BASE); in rkvdec_link_status_update()
131 val = readl(reg_base in rkvdec_link_status_update()
397 void __iomem *reg_base = dev->reg_base; rkvdec_link_send_task_to_hw() local
[all...]
H A Dmpp_rkvdec2_link.h80 void __iomem *reg_base; member
138 void __iomem *reg_base; member
H A Dmpp_common.h335 void __iomem *reg_base; member
643 writel(val, mpp->reg_base + reg); in mpp_write()
653 writel_relaxed(val, mpp->reg_base + reg); in mpp_write_relaxed()
663 val = readl(mpp->reg_base + reg); in mpp_read()
674 val = readl_relaxed(mpp->reg_base + reg); in mpp_read_relaxed()
/device/soc/rockchip/rk3588/kernel/drivers/video/rockchip/mpp/
H A Dmpp_rkvdec2_link.c109 void __iomem *reg_base = dev->reg_base; in rkvdec_link_status_update() local
115 error_ff1 = (readl(reg_base + RKVDEC_LINK_DEC_NUM_BASE) & in rkvdec_link_status_update()
117 enable_ff1 = readl(reg_base + RKVDEC_LINK_EN_BASE); in rkvdec_link_status_update()
119 dev->irq_status = readl(reg_base + RKVDEC_LINK_IRQ_BASE); in rkvdec_link_status_update()
120 dev->iova_curr = readl(reg_base + RKVDEC_LINK_CFG_ADDR_BASE); in rkvdec_link_status_update()
121 dev->link_mode = readl(reg_base + RKVDEC_LINK_MODE_BASE); in rkvdec_link_status_update()
122 dev->total = readl(reg_base + RKVDEC_LINK_TOTAL_NUM_BASE); in rkvdec_link_status_update()
123 dev->iova_next = readl(reg_base + RKVDEC_LINK_NEXT_ADDR_BASE); in rkvdec_link_status_update()
126 val = readl(reg_base in rkvdec_link_status_update()
398 void __iomem *reg_base = dev->reg_base; rkvdec_link_send_task_to_hw() local
[all...]
H A Dmpp_rkvdec2_link.h80 void __iomem *reg_base; member
138 void __iomem *reg_base; member
/device/soc/hisilicon/hi3861v100/sdk_liteos/app/demo/src/
H A Dapp_demo_spi.c40 hi_u32 reg_base; in app_demo_spi_print_reg() local
42 reg_base = HI_SSP0_REG_BASE; in app_demo_spi_print_reg()
44 reg_base = HI_SSP1_REG_BASE; in app_demo_spi_print_reg()
46 test_spi_printf("BASE_ADDR=%x", reg_base); in app_demo_spi_print_reg()
47 reg_val = hi_reg_read_val16(reg_base + 0x00); in app_demo_spi_print_reg()
49 reg_val = hi_reg_read_val16(reg_base + 0x04); in app_demo_spi_print_reg()
51 reg_val = hi_reg_read_val16(reg_base + 0x0c); in app_demo_spi_print_reg()
53 reg_val = hi_reg_read_val16(reg_base + 0x10); in app_demo_spi_print_reg()
55 reg_val = hi_reg_read_val16(reg_base + 0x14); in app_demo_spi_print_reg()
57 reg_val = hi_reg_read_val16(reg_base in app_demo_spi_print_reg()
[all...]
/device/soc/rockchip/common/vendor/drivers/firmware/
H A Drockchip_sip.c292 static struct pt_regs sip_fiq_debugger_get_pt_regs(void *reg_base, unsigned long sp_el1) in sip_fiq_debugger_get_pt_regs() argument
295 __maybe_unused struct sm_nsec_ctx *nsec_ctx = reg_base; in sip_fiq_debugger_get_pt_regs()
296 __maybe_unused struct gp_regs_ctx *gp_regs = reg_base; in sip_fiq_debugger_get_pt_regs()
303 memcpy(&fiq_pt_regs, reg_base, 0xf8); in sip_fiq_debugger_get_pt_regs()
306 memcpy(&fiq_pt_regs.pstate, reg_base + 0x110, 0x8); in sip_fiq_debugger_get_pt_regs()
310 memcpy(&fiq_pt_regs.pc, reg_base + 0x118, 0x8); in sip_fiq_debugger_get_pt_regs()
/device/soc/rockchip/rk3588/kernel/drivers/firmware/
H A Drockchip_sip.c294 static struct pt_regs sip_fiq_debugger_get_pt_regs(void *reg_base, in sip_fiq_debugger_get_pt_regs() argument
298 __maybe_unused struct sm_nsec_ctx *nsec_ctx = reg_base; in sip_fiq_debugger_get_pt_regs()
299 __maybe_unused struct gp_regs_ctx *gp_regs = reg_base; in sip_fiq_debugger_get_pt_regs()
306 memcpy(&fiq_pt_regs, reg_base, 8 * 31); in sip_fiq_debugger_get_pt_regs()
309 memcpy(&fiq_pt_regs.pstate, reg_base + 0x110, 8); in sip_fiq_debugger_get_pt_regs()
313 memcpy(&fiq_pt_regs.pc, reg_base + 0x118, 8); in sip_fiq_debugger_get_pt_regs()
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_reg.c29 readl(dp->reg_base); in analogix_dp_write()
30 writel(val, dp->reg_base + reg); in analogix_dp_write()
33 writel(val, dp->reg_base + reg); in analogix_dp_write()
39 readl(dp->reg_base + reg); in analogix_dp_read()
42 return readl(dp->reg_base + reg); in analogix_dp_read()
545 writel(0x19, dp->reg_base + ANALOIGX_DP_SSC_REG); in analogix_dp_ssc_enable()
550 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_ssc_enable()
552 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_ssc_enable()
554 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); in analogix_dp_ssc_enable()
561 reg = readl(dp->reg_base in analogix_dp_ssc_disable()
[all...]
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/compat/
H A Dhal_otp.c165 hi_void hal_efuse_otp_set_reg_base(hi_u8 *reg_base) in hal_efuse_otp_set_reg_base() argument
167 g_efuse_otp_reg_base = reg_base; in hal_efuse_otp_set_reg_base()

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