| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/hal/phy/hisiv100/regs/ |
| H A D | hdmi_reg_dphy.c | 39 hi_u32 *reg_addr = NULL; in hdmi_reg_sscin_bypass_en_set() local
42 reg_addr = (hi_u32 *)&(g_hdmi2tx_dphy_regs->ssc_in_set.u32); in hdmi_reg_sscin_bypass_en_set()
43 hdmitx_inssc.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_sscin_bypass_en_set()
45 hdmi_tx_reg_write(reg_addr, hdmitx_inssc.u32); in hdmi_reg_sscin_bypass_en_set()
52 hi_u32 *reg_addr = NULL; in hdmi_reg_pllfbmash111_en_set() local
55 reg_addr = (hi_u32 *)&(g_hdmi2tx_dphy_regs->ssc_in_set.u32); in hdmi_reg_pllfbmash111_en_set()
56 hdmitx_inssc.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_pllfbmash111_en_set()
58 hdmi_tx_reg_write(reg_addr, hdmitx_inssc.u32); in hdmi_reg_pllfbmash111_en_set()
65 hi_u32 *reg_addr = NULL; in hdmi_reg_dphy_rst_set() local
68 reg_addr in hdmi_reg_dphy_rst_set()
78 hi_u32 *reg_addr = NULL; hdmi_reg_aphy_data_clk_height_set() local
91 hi_u32 *reg_addr = NULL; hdmi_reg_aphy_data_clk_low_set() local
104 hi_u32 *reg_addr = NULL; hdmi_reg_divsel_set() local
117 hi_u32 *reg_addr = NULL; hdmi_reg_gc_txpll_pd_set() local
130 hi_u32 *reg_addr = NULL; hdmi_reg_gc_txpll_pd_get() local
140 hi_u32 *reg_addr = NULL; hdmi_reg_gc_pd_rxsense_set() local
153 hi_u32 *reg_addr = NULL; hdmi_reg_gc_pd_rxsense_get() local
163 hi_u32 *reg_addr = NULL; hdmi_reg_gc_pd_rterm_get() local
173 hi_u32 *reg_addr = NULL; hdmi_reg_gc_pd_rterm_set() local
186 hi_u32 *reg_addr = NULL; hdmi_reg_gc_pd_ldo_set() local
199 hi_u32 *reg_addr = NULL; hdmi_reg_gc_pd_ldo_get() local
209 hi_u32 *reg_addr = NULL; hdmi_reg_gc_pd_de_set() local
222 hi_u32 *reg_addr = NULL; hdmi_reg_gc_pd_de_get() local
232 hi_u32 *reg_addr = NULL; hdmi_reg_gc_pd_bist_set() local
245 hi_u32 *reg_addr = NULL; hdmi_reg_gc_pd_bist_get() local
256 hi_u32 *reg_addr = NULL; hdmi_reg_gc_pd_set() local
269 hi_u32 *reg_addr = NULL; hdmi_reg_gc_pd_get() local
279 hi_u32 *reg_addr = NULL; hdmi_reg_isel_main_de_clk_set() local
292 hi_u32 *reg_addr = NULL; hdmi_reg_isel_main_de_clk_get() local
302 hi_u32 *reg_addr = NULL; hdmi_reg_isel_main_d2_set() local
315 hi_u32 *reg_addr = NULL; hdmi_reg_isel_main_d1_set() local
328 hi_u32 *reg_addr = NULL; hdmi_reg_isel_main_d0_set() local
341 hi_u32 *reg_addr = NULL; hdmi_reg_isel_main_clk_set() local
354 hi_u32 *reg_addr = NULL; hdmi_reg_isel_pre_d0_set() local
367 hi_u32 *reg_addr = NULL; hdmi_reg_isel_pre_clk_set() local
380 hi_u32 *reg_addr = NULL; hdmi_reg_isel_main_de_d2_set() local
393 hi_u32 *reg_addr = NULL; hdmi_reg_isel_main_de_d2_get() local
404 hi_u32 *reg_addr = NULL; hdmi_reg_isel_main_de_d1_set() local
417 hi_u32 *reg_addr = NULL; hdmi_reg_isel_main_de_d1_get() local
428 hi_u32 *reg_addr = NULL; hdmi_reg_isel_main_de_d0_set() local
441 hi_u32 *reg_addr = NULL; hdmi_reg_isel_main_de_d0_get() local
452 hi_u32 *reg_addr = NULL; hdmi_reg_isel_main_clk_get() local
463 hi_u32 *reg_addr = NULL; hdmi_reg_isel_main_d0_get() local
474 hi_u32 *reg_addr = NULL; hdmi_reg_isel_pre_de_d1_set() local
487 hi_u32 *reg_addr = NULL; hdmi_reg_isel_pre_de_d0_set() local
500 hi_u32 *reg_addr = NULL; hdmi_reg_isel_pre_de_clk_set() local
513 hi_u32 *reg_addr = NULL; hdmi_reg_isel_pre_d2_set() local
526 hi_u32 *reg_addr = NULL; hdmi_reg_isel_pre_d1_set() local
539 hi_u32 *reg_addr = NULL; hdmi_reg_rsel_pre_de_d2_set() local
552 hi_u32 *reg_addr = NULL; hdmi_reg_rsel_pre_de_d1_set() local
565 hi_u32 *reg_addr = NULL; hdmi_reg_rsel_pre_de_d0_set() local
578 hi_u32 *reg_addr = NULL; hdmi_reg_rsel_pre_de_clk_set() local
591 hi_u32 *reg_addr = NULL; hdmi_reg_rsel_pre_d2_set() local
604 hi_u32 *reg_addr = NULL; hdmi_reg_rsel_pre_d1_set() local
617 hi_u32 *reg_addr = NULL; hdmi_reg_rsel_pre_d0_set() local
630 hi_u32 *reg_addr = NULL; hdmi_reg_rsel_pre_clk_set() local
643 hi_u32 *reg_addr = NULL; hdmi_reg_rsel_pre_clk_get() local
654 hi_u32 *reg_addr = NULL; hdmi_reg_rsel_pre_d0_get() local
665 hi_u32 *reg_addr = NULL; hdmi_reg_isel_pre_de_d2_set() local
678 hi_u32 *reg_addr = NULL; hdmi_reg_rt_d2_set() local
691 hi_u32 *reg_addr = NULL; hdmi_reg_test_set() local
704 hi_u32 *reg_addr = NULL; hdmi_reg_rt_d1_set() local
717 hi_u32 *reg_addr = NULL; hdmi_reg_rt_d0_set() local
730 hi_u32 *reg_addr = NULL; hdmi_reg_rt_clk_set() local
743 hi_u32 *reg_addr = NULL; hdmi_reg_gc_txpll_en_sscdiv_set() local
756 hi_u32 *reg_addr = NULL; hdmi_reg_txpll_icp_ictrl_set() local
769 hi_u32 *reg_addr = NULL; hdmi_reg_txpll_divsel_loop_set() local
782 hi_u32 *reg_addr = NULL; hdmi_reg_gc_txpll_test_set() local
795 hi_u32 *reg_addr = NULL; hdmi_reg_ssc_mode_fb_set() local
808 hi_u32 *reg_addr = NULL; hdmi_reg_load_fb_set() local
821 hi_u32 *reg_addr = NULL; hdmi_reg_fb_set() local
834 hi_u32 *reg_addr = NULL; hdmi_reg_span_fb_set() local
847 hi_u32 *reg_addr = NULL; hdmi_reg_span_fb_get() local
857 hi_u32 *reg_addr = NULL; hdmi_reg_step_fb_set() local
870 hi_u32 *reg_addr = NULL; hdmi_reg_step_fb_get() local
[all...] |
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/hal/ctrl/hisiv100/regs/ |
| H A D | hdmi_reg_video_path.c | 39 hi_u32 *reg_addr = NULL; in hdmi_reg_sync_polarity_set() local
42 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32); in hdmi_reg_sync_polarity_set()
43 gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_sync_polarity_set()
45 hdmi_tx_reg_write(reg_addr, gen_ctrl.u32); in hdmi_reg_sync_polarity_set()
52 hi_u32 *reg_addr = NULL; in hdmi_reg_sync_polarity_get() local
55 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32); in hdmi_reg_sync_polarity_get()
56 gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_sync_polarity_get()
62 hi_u32 *reg_addr = NULL; in hdmi_reg_timing_sel_set() local
65 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32); in hdmi_reg_timing_sel_set()
66 gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_timing_sel_set()
75 hi_u32 *reg_addr = NULL; hdmi_reg_timing_sel_get() local
85 hi_u32 *reg_addr = NULL; hdmi_reg_extmode_set() local
99 hi_u32 *reg_addr = NULL; hdmi_reg_extmode_get() local
109 hi_u32 *reg_addr = NULL; hdmi_reg_timing_gen_en_set() local
122 hi_u32 *reg_addr = NULL; hdmi_reg_timing_gen_en_get() local
132 hi_u32 *reg_addr = NULL; hdmi_reg_video_blank_en_set() local
145 hi_u32 *reg_addr = NULL; hdmi_reg_video_blank_en_get() local
155 hi_u32 *reg_addr = NULL; hdmi_reg_video_lp_disable_set() local
168 hi_u32 *reg_addr = NULL; hdmi_reg_video_lp_disable_get() local
178 hi_u32 *reg_addr = NULL; hdmi_reg_cbar_pattern_sel_set() local
191 hi_u32 *reg_addr = NULL; hdmi_reg_mask_pattern_en_set() local
204 hi_u32 *reg_addr = NULL; hdmi_reg_mask_pattern_en_get() local
214 hi_u32 *reg_addr = NULL; hdmi_reg_square_pattern_en_set() local
227 hi_u32 *reg_addr = NULL; hdmi_reg_square_pattern_en_get() local
237 hi_u32 *reg_addr = NULL; hdmi_reg_colorbar_en_set() local
250 hi_u32 *reg_addr = NULL; hdmi_reg_colorbar_en_get() local
261 hi_u32 *reg_addr = NULL; hdmi_reg_solid_pattern_en_set() local
274 hi_u32 *reg_addr = NULL; hdmi_reg_solid_pattern_en_get() local
284 hi_u32 *reg_addr = NULL; hdmi_reg_video_format_set() local
297 hi_u32 *reg_addr = NULL; hdmi_reg_video_format_get() local
308 hi_u32 *reg_addr = NULL; hdmi_reg_solid_pattern_cr_set() local
321 hi_u32 *reg_addr = NULL; hdmi_reg_solid_pattern_y_set() local
334 hi_u32 *reg_addr = NULL; hdmi_reg_solid_pattern_cb_set() local
347 hi_u32 *reg_addr = NULL; hdmi_reg_fdt_status_clear_set() local
360 hi_u32 *reg_addr = NULL; hdmi_reg_sync_polarity_force_set() local
373 hi_u32 *reg_addr = NULL; hdmi_reg_vsync_polarity_get() local
384 hi_u32 *reg_addr = NULL; hdmi_reg_hsync_polarity_get() local
395 hi_u32 *reg_addr = NULL; hdmi_reg_interlaced_get() local
406 hi_u32 *reg_addr = NULL; hdmi_reg_hsync_total_cnt_get() local
417 hi_u32 *reg_addr = NULL; hdmi_reg_hsync_active_cnt_get() local
427 hi_u32 *reg_addr = NULL; hdmi_reg_vsync_total_cnt_get() local
437 hi_u32 *reg_addr = NULL; hdmi_reg_vsync_active_cnt_get() local
448 hi_u32 *reg_addr = NULL; hdmi_reg_dwsm_vert_bypass_get() local
459 hi_u32 *reg_addr = NULL; hdmi_reg_dwsm_vert_en_get() local
470 hi_u32 *reg_addr = NULL; hdmi_reg_hori_filter_en_get() local
480 hi_u32 *reg_addr = NULL; hdmi_reg_dwsm_hori_en_get() local
491 hi_u32 *reg_addr = NULL; hdmi_reg_pxl_div_en_get() local
502 hi_u32 *reg_addr = NULL; hdmi_reg_demux_420_en_get() local
513 hi_u32 *reg_addr = NULL; hdmi_reg_inver_sync_get() local
524 hi_u32 *reg_addr = NULL; hdmi_reg_vmux_cr_sel_get() local
535 hi_u32 *reg_addr = NULL; hdmi_reg_vmux_cb_sel_get() local
546 hi_u32 *reg_addr = NULL; hdmi_reg_vmux_y_sel_get() local
557 hi_u32 *reg_addr = NULL; hdmi_reg_dither_mode_get() local
568 hi_u32 *reg_addr = NULL; hdmi_reg_dither_rnd_bypass_get() local
579 hi_u32 *reg_addr = NULL; hdmi_reg_csc_en_get() local
590 hi_u32 *reg_addr = NULL; hdmi_reg_csc_mode_get() local
600 hi_u32 *reg_addr = NULL; hdmi_reg_dither_mode_set() local
613 hi_u32 *reg_addr = NULL; hdmi_reg_dither_rnd_bypass_set() local
626 hi_u32 *reg_addr = NULL; hdmi_reg_csc_mode_set() local
639 hi_u32 *reg_addr = NULL; hdmi_reg_csc_saturate_en_set() local
652 hi_u32 *reg_addr = NULL; hdmi_reg_csc_en_set() local
665 hi_u32 *reg_addr = NULL; hdmi_reg_dwsm_vert_bypass_set() local
678 hi_u32 *reg_addr = NULL; hdmi_reg_dwsm_vert_en_set() local
691 hi_u32 *reg_addr = NULL; hdmi_reg_hori_filter_en_set() local
704 hi_u32 *reg_addr = NULL; hdmi_reg_dwsm_hori_en_set() local
717 hi_u32 *reg_addr = NULL; hdmi_reg_pxl_div_en_set() local
730 hi_u32 *reg_addr = NULL; hdmi_reg_demux_420_en_set() local
743 hi_u32 *reg_addr = NULL; hdmi_reg_inver_sync_set() local
756 hi_u32 *reg_addr = NULL; hdmi_reg_syncmask_en_set() local
769 hi_u32 *reg_addr = NULL; hdmi_reg_vmux_cr_sel_set() local
782 hi_u32 *reg_addr = NULL; hdmi_reg_vmux_cb_sel_set() local
795 hi_u32 *reg_addr = NULL; hdmi_reg_vmux_y_sel_set() local
[all...] |
| H A D | hdmi_reg_audio_path.c | 39 hi_u32 *reg_addr = NULL; in hdmi_reg_aud_spdif_en_set() local
42 reg_addr = (hi_u32 *)&(g_audio_path_regs->audio_ctl.u32); in hdmi_reg_aud_spdif_en_set()
43 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_aud_spdif_en_set()
45 hdmi_tx_reg_write(reg_addr, ctrl.u32); in hdmi_reg_aud_spdif_en_set()
52 hi_u32 *reg_addr = NULL; in hdmi_reg_aud_i2s_en_set() local
55 reg_addr = (hi_u32 *)&(g_audio_path_regs->audio_ctl.u32); in hdmi_reg_aud_i2s_en_set()
56 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_aud_i2s_en_set()
58 hdmi_tx_reg_write(reg_addr, ctrl.u32); in hdmi_reg_aud_i2s_en_set()
65 hi_u32 *reg_addr = NULL; in hdmi_reg_aud_layout_set() local
68 reg_addr in hdmi_reg_aud_layout_set()
78 hi_u32 *reg_addr = NULL; hdmi_reg_aud_mute_en_set() local
91 hi_u32 *reg_addr = NULL; hdmi_reg_aud_in_en_set() local
104 hi_u32 *reg_addr = NULL; hdmi_reg_i2s_ch_swap_set() local
117 hi_u32 *reg_addr = NULL; hdmi_reg_i2s_length_set() local
130 hi_u32 *reg_addr = NULL; hdmi_reg_i2s_vbit_set() local
143 hi_u32 *reg_addr = NULL; hdmi_reg_i2s_data_dir_set() local
156 hi_u32 *reg_addr = NULL; hdmi_reg_i2s_justify_set() local
169 hi_u32 *reg_addr = NULL; hdmi_reg_i2s_ws_polarity_set() local
182 hi_u32 *reg_addr = NULL; hdmi_reg_i2s_1st_shift_set() local
195 hi_u32 *reg_addr = NULL; hdmi_reg_i2s_hbra_on_set() local
208 hi_u32 *reg_addr = NULL; hdmi_reg_chst_byte3_clock_accuracy_set() local
221 hi_u32 *reg_addr = NULL; hdmi_reg_chst_byte3_fs_set() local
234 hi_u32 *reg_addr = NULL; hdmi_reg_chst_byte0_bset() local
247 hi_u32 *reg_addr = NULL; hdmi_reg_chst_byte0_aset() local
260 hi_u32 *reg_addr = NULL; hdmi_reg_chst_byte4_org_fs_set() local
273 hi_u32 *reg_addr = NULL; hdmi_reg_chst_byte4_length_set() local
286 hi_u32 *reg_addr = NULL; hdmi_reg_aud_fifo_hbr_mask_set() local
299 hi_u32 *reg_addr = NULL; hdmi_reg_aud_fifo_test_set() local
312 hi_u32 *reg_addr = NULL; hdmi_reg_acr_cts_hw_sw_sel_set() local
325 hi_u32 *reg_addr = NULL; hdmi_reg_acr_n_val_sw_set() local
338 hi_u32 *reg_addr = NULL; hdmi_reg_aud_spdif_en_get() local
348 hi_u32 *reg_addr = NULL; hdmi_reg_aud_i2s_en_get() local
358 hi_u32 *reg_addr = NULL; hdmi_reg_aud_layout_get() local
368 hi_u32 *reg_addr = NULL; hdmi_reg_aud_mute_en_get() local
378 hi_u32 *reg_addr = NULL; hdmi_reg_aud_in_en_get() local
388 hi_u32 *reg_addr = NULL; hdmi_reg_i2s_hbra_on_get() local
398 hi_u32 *reg_addr = NULL; hdmi_reg_chst_byte3_fs_get() local
408 hi_u32 *reg_addr = NULL; hdmi_reg_chst_byte4_org_fs_get() local
418 hi_u32 *reg_addr = NULL; hdmi_reg_chst_byte4_length_get() local
428 hi_u32 *reg_addr = NULL; hdmi_reg_aud_spdif_fs_get() local
438 hi_u32 *reg_addr = NULL; hdmi_reg_aud_length_get() local
448 hi_u32 *reg_addr = NULL; hdmi_reg_acr_cts_hw_sw_sel_get() local
458 hi_u32 *reg_addr = NULL; hdmi_reg_acr_n_val_sw_get() local
468 hi_u32 *reg_addr = NULL; hdmi_reg_acr_cts_val_sw_get() local
478 hi_u32 *reg_addr = NULL; hdmi_reg_acr_cts_val_hw_get() local
[all...] |
| H A D | hdmi_reg_ctrl.c | 39 hi_u32 *reg_addr = NULL; in hdmi_reg_tx_mcu_srst_req_set() local
42 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->pwd_rst_ctrl.u32); in hdmi_reg_tx_mcu_srst_req_set()
43 tx_pwd_rst.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_tx_mcu_srst_req_set()
45 hdmi_tx_reg_write(reg_addr, tx_pwd_rst.u32); in hdmi_reg_tx_mcu_srst_req_set()
52 hi_u32 *reg_addr = NULL; in hdmi_reg_tx_afifo_srst_req_set() local
55 reg_addr = (hi_u32 *)&(g_tx_ctrl_regs->pwd_rst_ctrl.u32); in hdmi_reg_tx_afifo_srst_req_set()
56 tx_pwd_rst.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_tx_afifo_srst_req_set()
58 hdmi_tx_reg_write(reg_addr, tx_pwd_rst.u32); in hdmi_reg_tx_afifo_srst_req_set()
65 hi_u32 *reg_addr = NULL; in hdmi_reg_tx_acr_srst_req_set() local
68 reg_addr in hdmi_reg_tx_acr_srst_req_set()
78 hi_u32 *reg_addr = NULL; hdmi_reg_tx_aud_srst_req_set() local
91 hi_u32 *reg_addr = NULL; hdmi_reg_tx_hdmi_srst_req_set() local
104 hi_u32 *reg_addr = NULL; hdmi_reg_tx_pwd_srst_req_set() local
117 hi_u32 *reg_addr = NULL; hdmi_reg_pwd_fifo_data_in_set() local
130 hi_u32 *reg_addr = NULL; hdmi_reg_pwd_data_out_cnt_set() local
143 hi_u32 *reg_addr = NULL; hdmi_reg_pwd_slave_seg_set() local
156 hi_u32 *reg_addr = NULL; hdmi_reg_pwd_slave_offset_set() local
169 hi_u32 *reg_addr = NULL; hdmi_reg_pwd_slave_addr_set() local
182 hi_u32 *reg_addr = NULL; hdmi_reg_pwd_mst_cmd_set() local
195 hi_u32 *reg_addr = NULL; hdmi_reg_cpu_ddc_req_set() local
208 hi_u32 *reg_addr = NULL; hdmi_reg_rdata_pwd_fifo_data_out_get() local
218 hi_u32 *reg_addr = NULL; hdmi_reg_pwd_fifo_data_out_get() local
228 hi_u32 *reg_addr = NULL; hdmi_reg_pwd_fifo_empty_get() local
238 hi_u32 *reg_addr = NULL; hdmi_reg_pwd_i2c_in_prog_get() local
248 hi_u32 *reg_addr = NULL; hdmi_reg_cpu_ddc_req_ack_get() local
[all...] |
| H A D | hdmi_reg_tx.c | 39 hi_u32 *reg_addr = NULL; in hdmi_reg_tmds_pack_mode_set() local
42 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->pack_fifo_ctrl.u32); in hdmi_reg_tmds_pack_mode_set()
43 tmp.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_tmds_pack_mode_set()
45 hdmi_tx_reg_write(reg_addr, tmp.u32); in hdmi_reg_tmds_pack_mode_set()
52 hi_u32 *reg_addr = NULL; in hdmi_reg_avi_pkt_header_hb_set() local
55 reg_addr = (hi_u32 *)&(g_tx_hdmi_regs->avi_head.u32); in hdmi_reg_avi_pkt_header_hb_set()
56 tmp.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_avi_pkt_header_hb_set()
60 hdmi_tx_reg_write(reg_addr, tmp.u32); in hdmi_reg_avi_pkt_header_hb_set()
68 hi_u32 *reg_addr = NULL; in hdmi_reg_avi_pkt0_low_set() local
71 reg_addr in hdmi_reg_avi_pkt0_low_set()
84 hi_u32 *reg_addr = NULL; hdmi_reg_avi_pkt0_high_set() local
100 hi_u32 *reg_addr = NULL; hdmi_reg_avi_pkt1_low_set() local
116 hi_u32 *reg_addr = NULL; hdmi_reg_avi_pkt1_high_set() local
132 hi_u32 *reg_addr = NULL; hdmi_reg_avi_pkt2_low_set() local
148 hi_u32 *reg_addr = NULL; hdmi_reg_avi_pkt2_high_set() local
164 hi_u32 *reg_addr = NULL; hdmi_reg_avi_pkt3_low_set() local
180 hi_u32 *reg_addr = NULL; hdmi_reg_avi_pkt3_high_set() local
195 hi_u32 *reg_addr = NULL; hdmi_reg_avi_pkt_header_hb_get() local
209 hi_u32 *reg_addr = NULL; hdmi_reg_avi_pkt0_low_get() local
224 hi_u32 *reg_addr = NULL; hdmi_reg_avi_pkt0_high_get() local
238 hi_u32 *reg_addr = NULL; hdmi_reg_avi_pkt1_low_get() local
253 hi_u32 *reg_addr = NULL; hdmi_reg_avi_pkt1_high_get() local
267 hi_u32 *reg_addr = NULL; hdmi_reg_avi_pkt2_low_get() local
282 hi_u32 *reg_addr = NULL; hdmi_reg_avi_pkt2_high_get() local
296 hi_u32 *reg_addr = NULL; hdmi_reg_avi_pkt3_low_get() local
311 hi_u32 *reg_addr = NULL; hdmi_reg_avi_pkt3_high_get() local
325 hi_u32 *reg_addr = NULL; hdmi_reg_audio_pkt_header_set() local
341 hi_u32 *reg_addr = NULL; hdmi_reg_audio_pkt0_low_set() local
358 hi_u32 *reg_addr = NULL; hdmi_reg_audio_pkt0_high_set() local
374 hi_u32 *reg_addr = NULL; hdmi_reg_audio_pkt1_low_set() local
391 hi_u32 *reg_addr = NULL; hdmi_reg_audio_pkt1_high_set() local
407 hi_u32 *reg_addr = NULL; hdmi_reg_audio_pkt2_low_set() local
424 hi_u32 *reg_addr = NULL; hdmi_reg_audio_pkt2_high_set() local
440 hi_u32 *reg_addr = NULL; hdmi_reg_audio_pkt3_low_set() local
457 hi_u32 *reg_addr = NULL; hdmi_reg_audio_pkt3_high_set() local
472 hi_u32 *reg_addr = NULL; hdmi_reg_aif_pkt_header_get() local
486 hi_u32 *reg_addr = NULL; hdmi_reg_aif_pkt0_low_get() local
501 hi_u32 *reg_addr = NULL; hdmi_reg_aif_pkt0_high_get() local
515 hi_u32 *reg_addr = NULL; hdmi_reg_aif_pkt1_low_get() local
530 hi_u32 *reg_addr = NULL; hdmi_reg_aif_pkt1_high_get() local
544 hi_u32 *reg_addr = NULL; hdmi_reg_aif_pkt2_low_get() local
559 hi_u32 *reg_addr = NULL; hdmi_reg_aif_pkt2_high_get() local
573 hi_u32 *reg_addr = NULL; hdmi_reg_aif_pkt3_low_get() local
588 hi_u32 *reg_addr = NULL; hdmi_reg_aif_pkt3_high_get() local
602 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt_header_set() local
618 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt0_low_set() local
634 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt0_high_set() local
650 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt1_low_set() local
666 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt1_high_set() local
682 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt2_low_set() local
698 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt2_high_set() local
714 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt3_low_set() local
730 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt3_high_set() local
745 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt_header_get() local
759 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt0_low_get() local
774 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt0_high_get() local
788 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt1_low_get() local
803 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt1_high_get() local
817 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt2_low_get() local
832 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt2_high_get() local
846 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt3_low_get() local
861 hi_u32 *reg_addr = NULL; hdmi_reg_gen_pkt3_high_get() local
875 hi_u32 *reg_addr = NULL; hdmi_reg_gamut_pkt_header_get() local
889 hi_u32 *reg_addr = NULL; hdmi_reg_gamut_pkt0_low_get() local
904 hi_u32 *reg_addr = NULL; hdmi_reg_gamut_pkt0_high_get() local
918 hi_u32 *reg_addr = NULL; hdmi_reg_gamut_pkt1_low_get() local
933 hi_u32 *reg_addr = NULL; hdmi_reg_gamut_pkt1_high_get() local
947 hi_u32 *reg_addr = NULL; hdmi_reg_gamut_pkt2_low_get() local
962 hi_u32 *reg_addr = NULL; hdmi_reg_gamut_pkt2_high_get() local
976 hi_u32 *reg_addr = NULL; hdmi_reg_gamut_pkt3_low_get() local
991 hi_u32 *reg_addr = NULL; hdmi_reg_gamut_pkt3_high_get() local
1005 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_header_set() local
1021 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt0_low_set() local
1037 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt0_high_set() local
1053 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt1_low_set() local
1069 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt1_high_set() local
1085 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt2_low_set() local
1101 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt2_high_set() local
1117 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt3_low_set() local
1133 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt3_high_set() local
1148 hi_u32 *reg_addr = NULL; hdmi_reg_cea_avi_rpt_en_set() local
1161 hi_u32 *reg_addr = NULL; hdmi_reg_cea_avi_en_set() local
1174 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt_header_get() local
1188 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt0_low_get() local
1203 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt0_high_get() local
1217 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt1_low_get() local
1232 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt1_high_get() local
1246 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt2_low_get() local
1261 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt2_high_get() local
1275 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt3_low_get() local
1290 hi_u32 *reg_addr = NULL; hdmi_reg_vsif_pkt3_high_get() local
1304 hi_u32 *reg_addr = NULL; hdmi_reg_cea_aud_rpt_en_set() local
1317 hi_u32 *reg_addr = NULL; hdmi_reg_cea_aud_en_set() local
1330 hi_u32 *reg_addr = NULL; hdmi_reg_cea_gen_rpt_en_set() local
1343 hi_u32 *reg_addr = NULL; hdmi_reg_cea_gen_en_set() local
1356 hi_u32 *reg_addr = NULL; hdmi_reg_cea_cp_rpt_cnt_set() local
1369 hi_u32 *reg_addr = NULL; hdmi_reg_cea_cp_rpt_en_set() local
1382 hi_u32 *reg_addr = NULL; hdmi_reg_cea_cp_en_set() local
1395 hi_u32 *reg_addr = NULL; hdmi_reg_cea_gamut_rpt_en_set() local
1408 hi_u32 *reg_addr = NULL; hdmi_reg_cea_gamut_en_set() local
1421 hi_u32 *reg_addr = NULL; hdmi_reg_cea_vsif_rpt_en_set() local
1434 hi_u32 *reg_addr = NULL; hdmi_reg_cea_vsif_en_set() local
1447 hi_u32 *reg_addr = NULL; hdmi_reg_eess_mode_en_set() local
1459 hi_u32 *reg_addr = NULL; hdmi_reg_hdmi_dvi_sel_set() local
1472 hi_u32 *reg_addr = NULL; hdmi_reg_dc_pkt_en_set() local
1485 hi_u32 *reg_addr = NULL; hdmi_reg_null_pkt_en_set() local
1497 hi_u32 *reg_addr = NULL; hdmi_reg_null_pkt_en_get() local
1508 hi_u32 *reg_addr = NULL; hdmi_reg_hdmi_mode_set() local
1521 hi_u32 *reg_addr = NULL; hdmi_reg_cp_clr_avmute_set() local
1534 hi_u32 *reg_addr = NULL; hdmi_reg_cp_set_avmute_set() local
1547 hi_u32 *reg_addr = NULL; hdmi_reg_enc_bypass_set() local
1560 hi_u32 *reg_addr = NULL; hdmi_reg_enc_scr_on_set() local
1573 hi_u32 *reg_addr = NULL; hdmi_reg_enc_hdmi2_on_set() local
1586 hi_u32 *reg_addr = NULL; hdmi_reg_tmds_pack_mode_get() local
1596 hi_u32 *reg_addr = NULL; hdmi_reg_pclk2tclk_stable_get() local
1606 hi_u32 *reg_addr = NULL; hdmi_reg_cea_avi_en_get() local
1616 hi_u32 *reg_addr = NULL; hdmi_reg_cea_aud_en_get() local
1626 hi_u32 *reg_addr = NULL; hdmi_reg_cea_gen_en_get() local
1636 hi_u32 *reg_addr = NULL; hdmi_reg_cea_cp_rpt_en_get() local
1646 hi_u32 *reg_addr = NULL; hdmi_reg_cea_gamut_en_get() local
1656 hi_u32 *reg_addr = NULL; hdmi_reg_cea_vsif_rpt_en_get() local
1666 hi_u32 *reg_addr = NULL; hdmi_reg_dc_pkt_en_get() local
1676 hi_u32 *reg_addr = NULL; hdmi_reg_hdmi_mode_get() local
1686 hi_u32 *reg_addr = NULL; hdmi_reg_cp_set_avmute_get() local
1696 hi_u32 *reg_addr = NULL; hdmi_reg_enc_scr_on_get() local
1706 hi_u32 *reg_addr = NULL; hdmi_reg_enc_hdmi2_on_get() local
[all...] |
| H A D | hdmi_reg_aon.c | 39 hi_u32 *reg_addr = NULL; in hdmi_reg_aon_intr_mask0_set() local
42 reg_addr = (hi_u32 *)&(g_tx_aon_regs->aon_irq_mask.u32); in hdmi_reg_aon_intr_mask0_set()
43 mask.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_aon_intr_mask0_set()
45 hdmi_tx_reg_write(reg_addr, mask.u32); in hdmi_reg_aon_intr_mask0_set()
52 hi_u32 *reg_addr = NULL; in hdmi_reg_aon_intr_stat1_set() local
55 reg_addr = (hi_u32 *)&(g_tx_aon_regs->aon_irq_state.u32); in hdmi_reg_aon_intr_stat1_set()
58 hdmi_tx_reg_write(reg_addr, state.u32); in hdmi_reg_aon_intr_stat1_set()
65 hi_u32 *reg_addr = NULL; in hdmi_reg_aon_intr_stat0_set() local
68 reg_addr = (hi_u32 *)&(g_tx_aon_regs->aon_irq_state.u32); in hdmi_reg_aon_intr_stat0_set()
71 hdmi_tx_reg_write(reg_addr, stat in hdmi_reg_aon_intr_stat0_set()
78 hi_u32 *reg_addr = NULL; hdmi_reg_dcc_man_en_set() local
91 hi_u32 *reg_addr = NULL; hdmi_reg_ddc_sda_oen_set() local
104 hi_u32 *reg_addr = NULL; hdmi_reg_ddc_scl_oen_set() local
117 hi_u32 *reg_addr = NULL; hdmi_reg_ddc_i2c_no_ack_get() local
127 hi_u32 *reg_addr = NULL; hdmi_reg_ddc_i2c_bus_low_get() local
137 hi_u32 *reg_addr = NULL; hdmi_reg_hpd_polarity_ctl_get() local
147 hi_u32 *reg_addr = NULL; hdmi_reg_phy_rx_sense_get() local
157 hi_u32 *reg_addr = NULL; hdmi_reg_hotplug_state_get() local
167 hi_u32 *reg_addr = NULL; hdmi_reg_aon_intr_stat1_get() local
177 hi_u32 *reg_addr = NULL; hdmi_reg_aon_intr_stat0_get() local
187 hi_u32 *reg_addr = NULL; hdmi_reg_ddc_sda_st_get() local
197 hi_u32 *reg_addr = NULL; hdmi_reg_ddc_scl_st_get() local
[all...] |
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/product/hi3516cv500/regs/ |
| H A D | hdmi_reg_crg.c | 48 hi_u32 *reg_addr = NULL;
in hdmi_reg_ssc_in_cken_set() local
51 reg_addr = (hi_u32 *)&(g_crg_regs->crg68.u32);
in hdmi_reg_ssc_in_cken_set()
52 peri_crg68.u32 = hdmi_tx_reg_read(reg_addr);
in hdmi_reg_ssc_in_cken_set()
54 hdmi_tx_reg_write(reg_addr, peri_crg68.u32);
in hdmi_reg_ssc_in_cken_set()
61 hi_u32 *reg_addr = NULL;
in hdmi_reg_ssc_bypass_cken_set() local
64 reg_addr = (hi_u32 *)&(g_crg_regs->crg68.u32);
in hdmi_reg_ssc_bypass_cken_set()
65 peri_crg68.u32 = hdmi_tx_reg_read(reg_addr);
in hdmi_reg_ssc_bypass_cken_set()
67 hdmi_tx_reg_write(reg_addr, peri_crg68.u32);
in hdmi_reg_ssc_bypass_cken_set()
74 hi_u32 *reg_addr = NULL;
in hdmi_reg_ctrl_osc_24m_cken_set() local
77 reg_addr in hdmi_reg_ctrl_osc_24m_cken_set()
87 hi_u32 *reg_addr = NULL; hdmi_reg_ctrl_cec_cken_set() local
100 hi_u32 *reg_addr = NULL; hdmi_reg_ctrl_os_cken_set() local
113 hi_u32 *reg_addr = NULL; hdmi_reg_ctrl_as_cken_set() local
126 hi_u32 *reg_addr = NULL; hdmi_reg_ctrl_bus_srst_req_set() local
139 hi_u32 *reg_addr = NULL; hdmi_reg_ctrl_srst_req_set() local
152 hi_u32 *reg_addr = NULL; hdmi_reg_ctrl_cec_srst_req_set() local
165 hi_u32 *reg_addr = NULL; hdmi_reg_ssc_srst_req_set() local
178 hi_u32 *reg_addr = NULL; hdmi_reg_ssc_clk_div_set() local
191 hi_u32 *reg_addr = NULL; hdmi_reg_pxl_cken_set() local
204 hi_u32 *reg_addr = NULL; reg_hdmi_crg_ssc_bypass_clk_sel_set() local
217 hi_u32 *reg_addr = NULL; hdmi_reg_hdmirx_phy_tmds_cken_set() local
230 hi_u32 *reg_addr = NULL; hdmi_reg_phy_srst_req_set() local
243 hi_u32 *reg_addr = NULL; hdmi_reg_phy_srst_req_get() local
253 hi_u32 *reg_addr = NULL; hdmi_reg_phy_tmds_srst_req_set() local
266 hi_u32 *reg_addr = NULL; hdmi_reg_phy_tmds_srst_req_get() local
276 hi_u32 *reg_addr = NULL; hdmi_reg_tmds_clk_div_set() local
289 hi_u32 *reg_addr = NULL; reg_hdmi_crg_tmds_clk_div_get() local
[all...] |
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/product/hi3516cv500/ |
| H A D | hdmi_product_define.c | 24 hi_void hdmi_tx_reg_write(hi_u32 *reg_addr, hi_u32 value) in hdmi_tx_reg_write() argument
26 *(volatile hi_u32 *)reg_addr = value; in hdmi_tx_reg_write()
30 hi_u32 hdmi_tx_reg_read(const hi_u32 *reg_addr) in hdmi_tx_reg_read() argument
32 return *(volatile hi_u32 *)(reg_addr); in hdmi_tx_reg_read()
35 hi_void hdmi_reg_write_u32(hi_u32 reg_addr, hi_u32 value) in hdmi_reg_write_u32() argument
39 addr = (volatile hi_u32 *)osal_ioremap_nocache((hi_u64)reg_addr, HDMI_REGISTER_SIZE); in hdmi_reg_write_u32()
44 hdmi_err("osal_ioremap_nocache addr=0x%x err!\n", reg_addr); in hdmi_reg_write_u32()
50 hi_u32 hdmi_reg_read_u32(hi_u32 reg_addr) in hdmi_reg_read_u32() argument
55 addr = (volatile hi_u32 *)osal_ioremap_nocache((hi_u64)reg_addr, HDMI_REGISTER_SIZE); in hdmi_reg_read_u32()
60 hdmi_err("osal_ioremap_nocache addr=0x%x\n err!\n", reg_addr); in hdmi_reg_read_u32()
[all...] |
| H A D | hdmi_product_define.h | 164 hi_void hdmi_tx_reg_write(hi_u32 *reg_addr, hi_u32 value);
166 hi_u32 hdmi_tx_reg_read(const hi_u32 *reg_addr);
168 hi_void hdmi_reg_write_u32(hi_u32 reg_addr, hi_u32 value);
170 hi_u32 hdmi_reg_read_u32(hi_u32 reg_addr);
|
| /device/soc/hisilicon/hi3861v100/sdk_liteos/app/demo/src/ |
| H A D | app_demo_i2c.c | 36 hi_u8 reg_addr = ES8311_REG_ADDR; in i2c_demo_send_data_init() local
38 g_send_data[0] = reg_addr; in i2c_demo_send_data_init()
39 g_send_data[1] = g_es8311_reg_array[reg_addr]; in i2c_demo_send_data_init()
41 reg_addr++; in i2c_demo_send_data_init()
42 g_send_data[2] = reg_addr; /* size 2 */ in i2c_demo_send_data_init()
43 g_send_data[3] = g_es8311_reg_array[reg_addr]; /* size 3 */ in i2c_demo_send_data_init()
|
| /device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/boot/ |
| H A D | init_regs.c | 38 unsigned int reg_addr; member
57 reg_val_r = (*(volatile unsigned *) (reg->reg_addr)); in reg_read()
77 reg_val_w = (*(volatile unsigned *) (reg->reg_addr)); in reg_write()
85 writel(reg_val_w,reg->reg_addr); in reg_write()
142 if ((!reg_table[i].reg_addr) && (!reg_table[i].value) in part_read_write()
|
| /device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/boot/ |
| H A D | init_regs.c | 39 unsigned int reg_addr; member
58 reg_val_r = (*(volatile unsigned *)((uintptr_t)(reg->reg_addr))); in reg_read()
78 reg_val_w = (*(volatile unsigned *)((uintptr_t)(reg->reg_addr))); in reg_write()
86 writel(reg_val_w, (uintptr_t)reg->reg_addr); in reg_write()
143 if ((!reg_table[i].reg_addr) && (!reg_table[i].value) in part_read_write()
|
| /device/soc/hisilicon/hi3751v350/sdk_linux/source/msp/drv/i2c/std_i2c/ |
| H A D | drv_i2c_intf.c | 44 hi_u32 reg_addr; member
143 p_data->reg_addr = (hi_u32)osal_strtoul(argv[3], NULL, 16); // 命令的第3个参数 字符串转成16进制的正整数 in i2c_proc_wr_read_get_dev_msg()
149 hi_dbg_print_h32(p_data->reg_addr); in i2c_proc_wr_read_get_dev_msg()
176 i2c_dev_msg.reg_addr, i2c_dev_msg.reg_addr_len, p_data, i2c_dev_msg.data_len); in i2c_proc_wr_read()
207 i2c_dev_msg.reg_addr, i2c_dev_msg.reg_addr_len, \ in i2c_proc_wr_read()
243 p_data->reg_addr = (hi_u32)osal_strtoul(argv[3], NULL, 16); // 命令的第3个参数 字符串转成16进制的正整数 in i2c_proc_wr_write_get_dev_msg()
270 hi_dbg_print_h32(p_data->reg_addr); in i2c_proc_wr_write_get_dev_msg()
294 i2c_dev_msg.reg_addr, i2c_dev_msg.reg_addr_len, send.send_data, send.len); in i2c_proc_wr_write()
318 i2c_dev_msg.reg_addr, i2c_dev_msg.reg_addr_len, in i2c_proc_wr_write()
|
| H A D | drv_i2c.c | 476 hi_u32 reg_addr = 0; in i2c_drv_write() local
507 reg_addr = i2c_reg_addr >> ((i2c_reg_addr_byte_num - i - 1) * 8); /* 8bit */ in i2c_drv_write()
508 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_TXR_REG), reg_addr); in i2c_drv_write()
547 hi_u32 reg_addr = 0; in i2c_drv_send_slave_by_int() local
560 reg_addr = i2c_info->i2c_reg_addr >> ((i2c_info->i2c_reg_addr_byte_num - i - 1) * 8); /* 8 bit */ in i2c_drv_send_slave_by_int()
561 i2c_write_reg((g_i2c_kernel_addr[i2c_info->i2c_num] + I2C_TXR_REG), reg_addr); in i2c_drv_send_slave_by_int()
578 hi_u32 reg_addr = 0; in i2c_drv_read() local
593 reg_addr = i2c_reg_addr >> ((i2c_reg_addr_byte_num - i - 1) * 8); /* 8 bit */ in i2c_drv_read()
594 i2c_drv_write_byte(i2c_num, reg_addr); in i2c_drv_read()
701 hi_u32 reg_addr in i2c_drv_write_sony() local
[all...] |
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/ |
| H A D | drv_hdmi_common.c | 315 hi_void hdmi_reg_write(volatile hi_void *reg_addr, hi_u32 value)
in hdmi_reg_write() argument
317 if (reg_addr != HI_NULL) {
in hdmi_reg_write()
318 *(volatile hi_u32 *)reg_addr = value;
in hdmi_reg_write()
322 hi_u32 hdmi_reg_read(volatile hi_void *reg_addr)
in hdmi_reg_read() argument
324 if (reg_addr == HI_NULL) {
in hdmi_reg_read()
327 return *(volatile hi_u32 *)reg_addr;
in hdmi_reg_read()
|
| /device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/drivers/io/ |
| H A D | hi_flashboot_io.c | 39 hi_u32 reg_addr; in hi_io_get_func() local
41 reg_addr = HI_IOCFG_REG_BASE + IO_MUX_REG_BASE_ADDR + ((hi_u32)id << 2); /* lift shift 2 bits */ in hi_io_get_func()
42 hi_reg_read(reg_addr, reg_val); in hi_io_get_func()
|
| /device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/ |
| H A D | wl_cfg_btcoex.c | 129 char reg_addr[8]; in dev_wlc_intvar_set_reg() local
131 bzero(reg_addr, sizeof(reg_addr)); in dev_wlc_intvar_set_reg()
132 memcpy((char *)®_addr[0], (char *)addr, 4); in dev_wlc_intvar_set_reg()
133 memcpy((char *)®_addr[4], (char *)val, 4); in dev_wlc_intvar_set_reg()
135 return (dev_wlc_bufvar_set(dev, name, (char *)®_addr[0], sizeof(reg_addr))); in dev_wlc_intvar_set_reg()
|
| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/ |
| H A D | mali_linux_trace.h | 466 TP_PROTO(u64 base_addr, u64 reg_addr, u64 *gpu_mem, unsigned int flags),
467 TP_ARGS(base_addr, reg_addr, gpu_mem, flags),
470 __field(u64, reg_addr)
477 __entry->reg_addr = reg_addr;
483 __entry->reg_addr, __entry->base_addr,
|
| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/ |
| H A D | mali_linux_trace.h | 312 mali_jit_report_gpu_mem, TP_PROTO(u64 base_addr, u64 reg_addr, u64 *gpu_mem, unsigned int flags),
313 TP_ARGS(base_addr, reg_addr, gpu_mem, flags),
314 TP_STRUCT__entry(__field(u64, base_addr) __field(u64, reg_addr)
317 TP_fast_assign(__entry->base_addr = base_addr; __entry->reg_addr = reg_addr;
319 TP_printk("start=0x%llx read GPU memory base=0x%llx values=%s report_flags=%s", __entry->reg_addr,
|
| /device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/ |
| H A D | isp_stats_v3x.c | 522 u32 *reg_addr, *raw_addr; in rkisp_stats_get_rawawb_meas_ddr() local
540 reg_addr = stats_vdev->stats_buf[rd_buf_idx].vaddr + offs + 0x2b00 + 0x710; in rkisp_stats_get_rawawb_meas_ddr()
542 rawawb->ro_rawawb_sum_rgain_nor[i] = reg_addr[(0x20 * i + 0x0) / 0x04]; in rkisp_stats_get_rawawb_meas_ddr()
543 rawawb->ro_rawawb_sum_bgain_nor[i] = reg_addr[(0x20 * i + 0x4) / 0x04]; in rkisp_stats_get_rawawb_meas_ddr()
544 rawawb->ro_rawawb_wp_num_nor[i] = reg_addr[(0x20 * i + 0x8) / 0x04]; in rkisp_stats_get_rawawb_meas_ddr()
545 rawawb->ro_wp_num2[i] = reg_addr[(0x20 * i + 0xc) / 0x04]; in rkisp_stats_get_rawawb_meas_ddr()
546 rawawb->ro_rawawb_sum_rgain_big[i] = reg_addr[(0x20 * i + 0x10) / 0x04]; in rkisp_stats_get_rawawb_meas_ddr()
547 rawawb->ro_rawawb_sum_bgain_big[i] = reg_addr[(0x20 * i + 0x14) / 0x04]; in rkisp_stats_get_rawawb_meas_ddr()
548 rawawb->ro_rawawb_wp_num_big[i] = reg_addr[(0x20 * i + 0x18) / 0x04]; in rkisp_stats_get_rawawb_meas_ddr()
552 value = reg_addr[( in rkisp_stats_get_rawawb_meas_ddr()
[all...] |
| H A D | isp_stats_v21.c | 485 u32 *reg_addr, *raw_addr; in rkisp_stats_get_rawawb_meas_ddr() local
497 reg_addr = stats_vdev->stats_buf[rd_buf_idx].vaddr + 0x2710; in rkisp_stats_get_rawawb_meas_ddr()
499 rawawb->ro_rawawb_sum_rgain_nor[i] = reg_addr[(0x20 * i + 0x0) / CIF_IMG_EFF_CTRL_MODE_EMBOSS_SHIFT]; in rkisp_stats_get_rawawb_meas_ddr()
500 rawawb->ro_rawawb_sum_bgain_nor[i] = reg_addr[(0x20 * i + 0x4) / CIF_IMG_EFF_CTRL_MODE_EMBOSS_SHIFT]; in rkisp_stats_get_rawawb_meas_ddr()
501 rawawb->ro_rawawb_wp_num_nor[i] = reg_addr[(0x20 * i + 0x8) / CIF_IMG_EFF_CTRL_MODE_EMBOSS_SHIFT]; in rkisp_stats_get_rawawb_meas_ddr()
502 rawawb->ro_rawawb_sum_rgain_big[i] = reg_addr[(0x20 * i + 0x10) / CIF_IMG_EFF_CTRL_MODE_EMBOSS_SHIFT]; in rkisp_stats_get_rawawb_meas_ddr()
503 rawawb->ro_rawawb_sum_bgain_big[i] = reg_addr[(0x20 * i + 0x14) / CIF_IMG_EFF_CTRL_MODE_EMBOSS_SHIFT]; in rkisp_stats_get_rawawb_meas_ddr()
504 rawawb->ro_rawawb_wp_num_big[i] = reg_addr[(0x20 * i + 0x18) / CIF_IMG_EFF_CTRL_MODE_EMBOSS_SHIFT]; in rkisp_stats_get_rawawb_meas_ddr()
508 value = reg_addr[(0x04 * i + 0xE0) / CIF_IMG_EFF_CTRL_MODE_EMBOSS_SHIFT]; in rkisp_stats_get_rawawb_meas_ddr()
|
| /device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/isp/ |
| H A D | isp_stats_v3x.c | 548 u32 *reg_addr, *raw_addr; in rkisp_stats_get_rawawb_meas_ddr() local
566 reg_addr = stats_vdev->stats_buf[rd_buf_idx].vaddr + offs + 0x2b00 + 0x710; in rkisp_stats_get_rawawb_meas_ddr()
569 reg_addr[(0x20 * i + 0x0) / 4]; in rkisp_stats_get_rawawb_meas_ddr()
571 reg_addr[(0x20 * i + 0x4) / 4]; in rkisp_stats_get_rawawb_meas_ddr()
573 reg_addr[(0x20 * i + 0x8) / 4]; in rkisp_stats_get_rawawb_meas_ddr()
575 reg_addr[(0x20 * i + 0xc) / 4]; in rkisp_stats_get_rawawb_meas_ddr()
577 reg_addr[(0x20 * i + 0x10) / 4]; in rkisp_stats_get_rawawb_meas_ddr()
579 reg_addr[(0x20 * i + 0x14) / 4]; in rkisp_stats_get_rawawb_meas_ddr()
581 reg_addr[(0x20 * i + 0x18) / 4]; in rkisp_stats_get_rawawb_meas_ddr()
585 value = reg_addr[( in rkisp_stats_get_rawawb_meas_ddr()
[all...] |
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/cbb/include/ |
| H A D | hi_i2c.h | 48 unsigned int reg_addr; member
|
| /device/soc/hisilicon/hi3516dv300/sdk_linux/include/ |
| H A D | hi_i2c.h | 48 unsigned int reg_addr; member
|
| /device/soc/hisilicon/hi3516dv300/sdk_liteos/include/ |
| H A D | hi_i2c.h | 48 unsigned int reg_addr; member
|