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Searched refs:pclk (Results 1 - 23 of 23) sorted by relevance

/device/soc/rockchip/common/sdk_linux/drivers/clocksource/
H A Dtimer-rockchip.c39 struct clk *pclk; member
134 struct clk *pclk; in rk_timer_probe() local
150 pclk = of_clk_get_by_name(np, "pclk"); in rk_timer_probe()
151 if (IS_ERR(pclk)) { in rk_timer_probe()
152 ret = PTR_ERR(pclk); in rk_timer_probe()
153 pr_err("Failed to get pclk for '%s'\n", TIMER_NAME); in rk_timer_probe()
157 ret = clk_prepare_enable(pclk); in rk_timer_probe()
159 pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME); in rk_timer_probe()
162 timer->pclk in rk_timer_probe()
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/device/soc/rockchip/common/sdk_linux/drivers/pwm/
H A Dpwm-rockchip.c42 struct clk *pclk; member
83 ret = clk_enable(pc->pclk); in rockchip_pwm_get_state()
105 clk_disable(pc->pclk); in rockchip_pwm_get_state()
235 ret = clk_enable(pc->pclk); in rockchip_pwm_apply()
263 clk_disable(pc->pclk); in rockchip_pwm_apply()
380 pc->pclk = devm_clk_get(&pdev->dev, "pclk"); in rockchip_pwm_probe()
382 pc->pclk = pc->clk; in rockchip_pwm_probe()
385 if (IS_ERR(pc->pclk)) { in rockchip_pwm_probe()
386 ret = PTR_ERR(pc->pclk); in rockchip_pwm_probe()
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/device/soc/rockchip/rk3566/sdk_linux/drivers/iio/adc/
H A Drockchip_saradc.c48 struct clk *pclk; member
259 clk_disable_unprepare(info->pclk); in rockchip_saradc_pclk_disable()
441 info->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); in rockchip_saradc_probe()
442 if (IS_ERR(info->pclk)) { in rockchip_saradc_probe()
443 dev_err(&pdev->dev, "failed to get pclk\n"); in rockchip_saradc_probe()
444 return PTR_ERR(info->pclk); in rockchip_saradc_probe()
491 ret = clk_prepare_enable(info->pclk); in rockchip_saradc_probe()
493 dev_err(&pdev->dev, "failed to enable pclk\n"); in rockchip_saradc_probe()
550 clk_disable_unprepare(info->pclk); in rockchip_saradc_suspend()
567 ret = clk_prepare_enable(info->pclk); in rockchip_saradc_resume()
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/device/soc/rockchip/common/sdk_linux/drivers/tty/serial/8250/
H A D8250_dw.c48 struct clk *pclk; member
623 data->pclk = devm_clk_get_optional(dev, "apb_pclk"); in dw8250_probe()
624 if (IS_ERR(data->pclk)) { in dw8250_probe()
625 err = PTR_ERR(data->pclk); in dw8250_probe()
629 err = clk_prepare_enable(data->pclk); in dw8250_probe()
695 clk_disable_unprepare(data->pclk); in dw8250_probe()
720 clk_disable_unprepare(data->pclk); in dw8250_remove()
779 clk_disable_unprepare(data->pclk); in dw8250_runtime_suspend()
788 clk_prepare_enable(data->pclk); in dw8250_runtime_resume()
/device/soc/rockchip/common/vendor/drivers/phy/
H A Dphy-rockchip-naneng-edp.c69 struct clk *pclk; member
246 clk_prepare_enable(edpphy->pclk); in rockchip_edp_phy_power_on()
286 clk_disable_unprepare(edpphy->pclk); in rockchip_edp_phy_power_off()
327 edpphy->pclk = devm_clk_get(dev, "pclk"); in rockchip_edp_phy_probe()
328 if (IS_ERR(edpphy->pclk)) { in rockchip_edp_phy_probe()
329 ret = PTR_ERR(edpphy->pclk); in rockchip_edp_phy_probe()
330 dev_err(dev, "failed to get pclk: %d\n", ret); in rockchip_edp_phy_probe()
H A Dphy-rockchip-inno-hdmi-phy.c181 struct clk *pclk; member
226 * freq div is needed. For example, pclk 88.75 Mhz and tmdsclk
763 inno->pclk = devm_clk_register(dev, &inno->hw); in inno_hdmi_phy_clk_register()
764 if (IS_ERR(inno->pclk)) { in inno_hdmi_phy_clk_register()
765 ret = PTR_ERR(inno->pclk); in inno_hdmi_phy_clk_register()
770 ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->pclk); in inno_hdmi_phy_clk_register()
/device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-edp.c73 struct clk *pclk; member
268 clk_prepare_enable(edpphy->pclk); in rockchip_edp_phy_power_on()
312 clk_disable_unprepare(edpphy->pclk); in rockchip_edp_phy_power_off()
351 edpphy->pclk = devm_clk_get(dev, "pclk"); in rockchip_edp_phy_probe()
352 if (IS_ERR(edpphy->pclk)) { in rockchip_edp_phy_probe()
353 ret = PTR_ERR(edpphy->pclk); in rockchip_edp_phy_probe()
354 dev_err(dev, "failed to get pclk: %d\n", ret); in rockchip_edp_phy_probe()
H A Dphy-rockchip-samsung-dcphy.c180 struct clk *pclk; member
1877 samsung->pclk = devm_clk_get(dev, "pclk"); in samsung_mipi_dcphy_probe()
1878 if (IS_ERR(samsung->pclk)) { in samsung_mipi_dcphy_probe()
1879 dev_err(dev, "failed to get pclk\n"); in samsung_mipi_dcphy_probe()
1880 return PTR_ERR(samsung->pclk); in samsung_mipi_dcphy_probe()
1933 clk_disable_unprepare(samsung->pclk); in samsung_mipi_dcphy_runtime_suspend()
1943 clk_prepare_enable(samsung->pclk); in samsung_mipi_dcphy_runtime_resume()
H A Dphy-rockchip-inno-hdmi-phy.c184 struct clk *pclk; member
233 * freq div is needed. For example, pclk 88.75 Mhz and tmdsclk
658 inno->pclk = devm_clk_register(dev, &inno->hw); in inno_hdmi_phy_clk_register()
659 if (IS_ERR(inno->pclk)) { in inno_hdmi_phy_clk_register()
660 ret = PTR_ERR(inno->pclk); in inno_hdmi_phy_clk_register()
665 ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->pclk); in inno_hdmi_phy_clk_register()
/device/soc/rockchip/common/sdk_linux/drivers/i2c/busses/
H A Di2c-rk3x.c206 * @pclk: Bus clk for rk3399
230 struct clk *pclk; member
931 clk_enable(i2c->pclk); in rk3x_i2c_adapt_div()
942 clk_disable(i2c->pclk); in rk3x_i2c_adapt_div()
1108 clk_enable(i2c->pclk); in rk3x_i2c_xfer_common()
1151 clk_disable(i2c->pclk); in rk3x_i2c_xfer_common()
1391 i2c->pclk = i2c->clk; in rk3x_i2c_probe()
1394 i2c->pclk = devm_clk_get(&pdev->dev, "pclk"); in rk3x_i2c_probe()
1401 if (IS_ERR(i2c->pclk)) { in rk3x_i2c_probe()
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/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
H A Dinno_hdmi.c55 struct clk *pclk; member
785 hdmi->pclk = devm_clk_get(hdmi->dev, "pclk"); in inno_hdmi_bind()
786 if (IS_ERR(hdmi->pclk)) { in inno_hdmi_bind()
787 DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI pclk clk\n"); in inno_hdmi_bind()
788 return PTR_ERR(hdmi->pclk); in inno_hdmi_bind()
791 ret = clk_prepare_enable(hdmi->pclk); in inno_hdmi_bind()
793 DRM_DEV_ERROR(hdmi->dev, "Cannot enable HDMI pclk clock: %d\n", ret); in inno_hdmi_bind()
818 hdmi->tmds_rate = clk_get_rate(hdmi->pclk); in inno_hdmi_bind()
843 clk_disable_unprepare(hdmi->pclk); in inno_hdmi_bind()
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H A Dcdn-dp-core.h85 struct clk *pclk; member
H A Ddw-mipi-dsi-rockchip.c262 struct clk *pclk; member
1080 dsi->pclk = devm_clk_get(dev, "pclk"); in dw_mipi_dsi_rockchip_probe()
1081 if (IS_ERR(dsi->pclk)) { in dw_mipi_dsi_rockchip_probe()
1082 ret = PTR_ERR(dsi->pclk); in dw_mipi_dsi_rockchip_probe()
1083 dev_err(dev, "Unable to get pclk: %d\n", ret); in dw_mipi_dsi_rockchip_probe()
1177 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_runtime_suspend()
1190 clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_runtime_resume()
H A Dcdn-dp-core.c83 ret = clk_prepare_enable(dp->pclk); in cdn_dp_clk_enable()
85 DRM_DEV_ERROR(dp->dev, "cannot enable dp pclk %d\n", ret); in cdn_dp_clk_enable()
125 clk_disable_unprepare(dp->pclk); in cdn_dp_clk_enable()
133 clk_disable_unprepare(dp->pclk); in cdn_dp_clk_disable()
686 dp->pclk = devm_clk_get(dev, "pclk"); in cdn_dp_parse_dt()
687 if (IS_ERR(dp->pclk)) { in cdn_dp_parse_dt()
688 DRM_DEV_ERROR(dev, "cannot get pclk\n"); in cdn_dp_parse_dt()
689 return PTR_ERR(dp->pclk); in cdn_dp_parse_dt()
H A Ddw-mipi-dsi2-rockchip.c241 struct clk *pclk; member
1451 dsi2->pclk = devm_clk_get(dev, "pclk"); in dw_mipi_dsi2_probe()
1452 if (IS_ERR(dsi2->pclk)) { in dw_mipi_dsi2_probe()
1453 ret = PTR_ERR(dsi2->pclk); in dw_mipi_dsi2_probe()
1454 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret); in dw_mipi_dsi2_probe()
1533 clk_disable_unprepare(dsi2->pclk); in dw_mipi_dsi2_runtime_suspend()
1543 clk_prepare_enable(dsi2->pclk); in dw_mipi_dsi2_runtime_resume()
H A Ddw_hdmi-rockchip.c181 struct clk *pclk; member
1444 hdmi->pclk = devm_clk_get_optional(hdmi->dev, "pclk"); in rockchip_hdmi_parse_dt()
1445 if (IS_ERR(hdmi->pclk)) { in rockchip_hdmi_parse_dt()
1446 dev_err_probe(hdmi->dev, PTR_ERR(hdmi->pclk), "failed to get pclk clock\n"); in rockchip_hdmi_parse_dt()
1447 return PTR_ERR(hdmi->pclk); in rockchip_hdmi_parse_dt()
2905 ret = clk_prepare_enable(hdmi->pclk); in dw_hdmi_rockchip_bind()
2907 dev_err(hdmi->dev, "Failed to enable HDMI pclk: %d\n", ret); in dw_hdmi_rockchip_bind()
3034 clk_disable_unprepare(hdmi->pclk); in dw_hdmi_rockchip_bind()
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H A Drockchip_drm_vop2.c688 struct clk *pclk; member
2505 ret = clk_enable(vop2->pclk); in vop2_core_clks_enable()
2521 clk_disable(vop2->pclk); in vop2_core_clks_disable()
3095 ret = clk_prepare_enable(vop2->pclk); in vop2_core_clks_prepare_enable()
3097 dev_err(vop2->dev, "failed to enable pclk - %d\n", ret); in vop2_core_clks_prepare_enable()
3325 clk_disable_unprepare(vop2->pclk); in vop2_disable()
8660 vop2->pclk = devm_clk_get_optional(vop2->dev, "pclk_vop"); in vop2_bind()
8661 if (IS_ERR(vop2->pclk)) { in vop2_bind()
8662 DRM_DEV_ERROR(vop2->dev, "failed to get pclk source\n"); in vop2_bind()
8663 return PTR_ERR(vop2->pclk); in vop2_bind()
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/device/soc/rockchip/common/sdk_linux/include/linux/
H A Dstmmac.h190 struct clk *pclk; member
/device/soc/rockchip/common/vendor/drivers/gpu/drm/rockchip/ebc-dev/tcon/
H A Debc_tcon.h87 struct clk *pclk; member
/device/soc/rockchip/common/vendor/drivers/rockchip/
H A Drk_fiq_debugger.c920 struct clk *pclk; in rk_fiqdbg_probe() local
987 pclk = of_clk_get_by_name(np, "apb_pclk"); in rk_fiqdbg_probe()
989 if (unlikely(IS_ERR(clk)) || unlikely(IS_ERR(pclk))) { in rk_fiqdbg_probe()
995 clk_prepare_enable(pclk); in rk_fiqdbg_probe()
/device/soc/rockchip/rk3588/kernel/drivers/soc/rockchip/
H A Drk_fiq_debugger.c943 struct clk *pclk; in rk_fiqdbg_probe() local
1002 pclk = of_clk_get_by_name(np, "apb_pclk"); in rk_fiqdbg_probe()
1004 if (unlikely(IS_ERR(clk)) || unlikely(IS_ERR(pclk))) { in rk_fiqdbg_probe()
1010 clk_prepare_enable(pclk); in rk_fiqdbg_probe()
/device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/
H A Ddw-mipi-dsi2-rockchip.c242 struct clk *pclk; member
1441 dsi2->pclk = devm_clk_get(dev, "pclk"); in dw_mipi_dsi2_probe()
1442 if (IS_ERR(dsi2->pclk)) { in dw_mipi_dsi2_probe()
1443 ret = PTR_ERR(dsi2->pclk); in dw_mipi_dsi2_probe()
1444 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret); in dw_mipi_dsi2_probe()
1528 clk_disable_unprepare(dsi2->pclk); in dw_mipi_dsi2_runtime_suspend()
1538 clk_prepare_enable(dsi2->pclk); in dw_mipi_dsi2_runtime_resume()
H A Drockchip_drm_vop2.c712 struct clk *pclk; member
2495 ret = clk_enable(vop2->pclk); in vop2_core_clks_enable()
2510 clk_disable(vop2->pclk); in vop2_core_clks_disable()
3090 ret = clk_prepare_enable(vop2->pclk); in vop2_core_clks_prepare_enable()
3092 dev_err(vop2->dev, "failed to enable pclk - %d\n", ret); in vop2_core_clks_prepare_enable()
3327 clk_disable_unprepare(vop2->pclk); in vop2_disable()
8765 vop2->pclk = devm_clk_get_optional(vop2->dev, "pclk_vop"); in vop2_bind()
8766 if (IS_ERR(vop2->pclk)) { in vop2_bind()
8767 DRM_DEV_ERROR(vop2->dev, "failed to get pclk source\n"); in vop2_bind()
8768 return PTR_ERR(vop2->pclk); in vop2_bind()
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