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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/tde/driver/src/adp/tde_v2_0/
H A Dtde_adp.h131 hi_u32 src1_fmt : 6; /* [5..0] */
132 hi_u32 src1_argb_order : 5; /* [10..6] */
133 hi_u32 src1_cbcr_order : 1; /* [11] */
134 hi_u32 src1_rgb_exp : 2; /* [13..12] */
135 hi_u32 reserved_0 : 1; /* [14] */
136 hi_u32 src1_rgb_mode : 1; /* [15] */
137 hi_u32 reserved_1 : 2; /* [17..16] */
138 hi_u32 src1_alpha_range : 1; /* [18] */
139 hi_u32 src1_v_scan_ord : 1; /* [19] */
140 hi_u32 src1_h_scan_or
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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/drivers/core/include/
H A Ddrv_symc.h159 hi_u32 id;
163 hi_u32 klen;
166 hi_u32 inlen;
167 hi_u32 inaddr;
168 hi_u32 outlen;
169 hi_u32 outaddr;
175 hi_u32 outintcnt;
181 hi_u32 aes_ecb : 1; /* Support AES ECB */
182 hi_u32 aes_cbc : 1; /* Support AES CBC */
183 hi_u32 aes_cf
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/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/wal/
H A Dwal_customize.h356 hi_u32 init_cfg_nvram_max_txpwr_base_2p4g;
358 hi_u32 init_cfg_nvram_params0;
359 hi_u32 init_cfg_nvram_params1;
360 hi_u32 init_cfg_nvram_params2;
361 hi_u32 init_cfg_nvram_params3;
365 hi_u32 init_cfg_country_code;
366 hi_u32 init_cfg_ampdu_tx_max_num;
367 hi_u32 init_cfg_used_mem_for_start;
368 hi_u32 init_cfg_used_mem_for_stop;
369 hi_u32 init_cfg_rx_ack_limi
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/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/oal/
H A Dwlan_mib.h1253 hi_u32 dot11_authentication_response_time_out; /* dot11AuthenticationResponseTimeOut Unsigned32, */
1257 hi_u32 dot11_beacon_period; /* dot11BeaconPeriod Unsigned32, */
1258 hi_u32 dot11_dtim_period; /* dot11DTIMPeriod Unsigned32, */
1259 hi_u32 dot11_association_response_time_out; /* dot11AssociationResponseTimeOut Unsigned32, */
1270 hi_u32 dot11_association_sa_query_maximum_timeout; /* dot11AssociationSAQueryMaximumTimeout Unsigned32, */
1271 hi_u32 dot11_association_sa_query_retry_timeout; /* dot11AssociationSAQueryRetryTimeout Unsigned32, */
1331 hi_u32 dot11_multi_domain_capability_index; /* dot11MultiDomainCapabilityIndex Unsigned32, */
1332 hi_u32 dot11_first_channel_number; /* dot11FirstChannelNumber Unsigned32, */
1333 hi_u32 dot11_numberof_channels; /* dot11NumberofChannels Unsigned32, */
1344 hi_u32 dot11_spectrum_management_inde
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H A Dplat_pm_wlan.h112 typedef hi_u32 (*wifi_srv_get_pm_pause_func)(hi_void);
127 volatile hi_u32 vote_status; /* 0:sleep 1: work，每一bit代表一个投票 */
134 hi_u32 packet_cnt; /* 睡眠周期内统计的packet个数 */
135 hi_u32 wdg_timeout_cnt; /* timeout check cnt */
136 hi_u32 wdg_timeout_curr_cnt; /* timeout check current cnt */
137 hi_u32 slpreq_flag;
138 hi_u32 slpack;
149 hi_u32 open_cnt;
150 hi_u32 close_cnt;
151 hi_u32 close_done_callbac
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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/drivers/core/
H A Ddrv_symc_v200.h69 hi_u32 reserved_0 : 28; /* [27..0] */
70 hi_u32 spacc_core_auto_cken_bypass : 1; /* [28] */
71 hi_u32 spacc_rft_mem_wr_clk_gt_en : 1; /* [29] */
72 hi_u32 spacc_rft_mem_rd_clk_gt_en : 1; /* [30] */
73 hi_u32 spacc_rfs_mem_clk_gt_en : 1; /* [31] */
77 hi_u32 u32;
84 hi_u32 cipher_sec_chn_cfg : 8; /* [7..0] */
85 hi_u32 cipher_sec_chn_cfg_lock : 1; /* [8] */
86 hi_u32 reserved_0 : 7; /* [15..9] */
87 hi_u32 hash_sec_chn_cf
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H A Ddrv_hash_v200.h49 hi_u32 cipher_sec_chn_cfg : 8; /* [7..0] */
50 hi_u32 cipher_sec_chn_cfg_lock : 1; /* [8] */
51 hi_u32 reserved_0 : 7; /* [15..9] */
52 hi_u32 hash_sec_chn_cfg : 8; /* [23..16] */
53 hi_u32 hash_sec_chn_cfg_lock : 1; /* [24] */
54 hi_u32 reserved_1 : 7; /* [31..25] */
58 hi_u32 u32;
65 hi_u32 hash_ch0_start : 1; /* [0] */
66 hi_u32 hash_ch0_agl_sel : 3; /* [3..1] */
67 hi_u32 hash_ch0_hmac_calc_ste
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H A Ddrv_symc_v100.h111 hi_u32 decrypt : 1; /* [0] */
112 hi_u32 mode : 3; /* [3..1] */
113 hi_u32 alg_sel : 2; /* [5..4] */
114 hi_u32 width : 2; /* [7..6] */
115 hi_u32 reserved_1 : 1; /* [8] */
116 hi_u32 key_length : 2; /* [10..9] */
117 hi_u32 reserved_2 : 2; /* [12..11] */
118 hi_u32 key_sel : 1; /* [13] */
119 hi_u32 key_adder : 3; /* [16..14] */
120 hi_u32 reserved_
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/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H A Dhi_crash.h121 hi_u32 mepc;
122 hi_u32 ra;
123 hi_u32 sp;
124 hi_u32 gp;
125 hi_u32 tp;
126 hi_u32 t0;
127 hi_u32 t1;
128 hi_u32 t2;
129 hi_u32 s0;
130 hi_u32 s
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H A Dhi_hook_fuc.h27 typedef hi_u32 (*fuc_type_name(hi_task_create))(hi_u32 *taskid,
32 typedef hi_u32 (*fuc_type_name(hi_task_delete))(hi_u32 taskid);
34 typedef hi_u32 (*fuc_type_name(hi_task_suspend))(hi_u32 taskid);
36 typedef hi_u32 (*fuc_type_name(hi_task_resume))(hi_u32 taskid);
38 typedef hi_u32 (*fuc_type_name(hi_task_get_priority))(hi_u32 taski
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H A Dhi_diag.h48 HI_EXTERN hi_u32 hi_diag_register_connect_notify(hi_diag_connect_f connect_notify_func);
93 HI_EXTERN hi_u32 hi_diag_register_cmd(const hi_diag_cmd_reg_obj* cmd_tbl, hi_u16 cmd_num);
131 HI_EXTERN hi_u32 hi_diag_report_packet(hi_u16 cmd_id, hi_u8 instance_id, hi_pbyte buffer,
161 HI_EXTERN hi_u32 hi_diag_send_ack_packet(hi_u16 cmd_id, hi_u8 instance_id, hi_pvoid buffer, hi_u16 buffer_size);
186 HI_EXTERN hi_u32 hi_diag_register_cmd_notify(hi_diag_cmd_notify_f cmd_notify_func);
210 HI_EXTERN hi_u32 hi_diag_set_uart_param(hi_uart_idx uart_port, hi_uart_attribute uart_cfg);
230 HI_EXTERN hi_u32 hi_diag_init(hi_void);
273 hi_u32 data0;
274 hi_u32 data1;
275 hi_u32 data
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H A Dhi_task.h36 hi_u32 id; /**< Task ID.CNcomment:任务ID CNend */
41 hi_u32 event_stru[3]; /**< Event: 3 nums.CNcomment:3个事件CNend */
42 hi_u32 event_mask; /**< Event mask.CNcomment:事件掩码CNend */
43 hi_u32 stack_size; /**< Task stack size.CNcomment:栈大小CNend */
44 hi_u32 top_of_stack; /**< Task stack top.CNcomment:栈顶CNend */
45 hi_u32 bottom_of_stack; /**< Task stack bottom.CNcomment:栈底CNend */
46 hi_u32 mstatus; /**< Task current mstatus.CNcomment:当前mstatusCNend */
47 hi_u32 mepc; /**< Task current mepc.CNcomment:当前mepc.CNend */
48 hi_u32 tp; /**< Task current tp.CNcomment:当前tp.CNend */
49 hi_u32 r
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H A Dhi_partition_table.h51 hi_u32 addr : 24; /**< Flash partition address.The value is 16 MB.If the address is in reverse order,
54 hi_u32 id : 7; /**< Flash partition ID.CNcomment:Flash区ID.CNend */
55 hi_u32 dir : 1; /**< Flash area storage direction.0:regular.1: reversed.CNcomment:Flash区存放方向。
58 hi_u32 size : 24; /**< Size of the parition(Unit:byte).CNcomment:Flash分区大小（单位：byte）CNend */
59 hi_u32 reserve : 8; /**< Reserved. CNcomment:保留区CNend */
61 hi_u32 addition; /**< Supplementary information about the flash partition, such as the address of the
111 hi_u32 hi_flash_partition_init(hi_void);
121 * @param addr [OUT] type #hi_u32*, Address of HiLink partition.CNcomment:HiLink分区地址。CNend
122 * @param size [OUT] type #hi_u32*, Size of HiLink partitioin, in bytes.CNcomment:HiLink分区大小，单位byte。CNend
131 hi_u32 hi_get_hilink_partition_tabl
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H A Dhi_isr.h33 hi_u32 r4;
34 hi_u32 r5;
35 hi_u32 r6;
36 hi_u32 r7;
37 hi_u32 r8;
38 hi_u32 r9;
39 hi_u32 r10;
40 hi_u32 r11;
41 hi_u32 pri_mask;
43 hi_u32 s
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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hifb/drv/include/
H A Dhifb_vou_drv.h36 hi_u32 curosr_buf_size; /* For soft cursor */
43 hi_u32 curosr_buf_size; /* For soft cursor */
48 typedef hi_s32 (*intvgscallback)(hi_u32 call_mod_id, hi_u32 call_dev_id, hi_u32 call_chn_id, hi_void *job_data);
69 typedef hi_u32 hifb_layer_id; /* start from 0 */
72 hi_bool is_hd_layer(hi_u32 layer_id);
73 hi_bool is_sd_layer(hi_u32 layer_id);
74 hi_bool is_ad_layer(hi_u32 layer_id);
75 hi_bool is_cursor_layer(hi_u32 layer_i
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/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/mac/hmac/
H A Dhmac_config.h37 typedef hi_u32 (*wal_config_get_func)(mac_vap_stru *pst_mac_vap, hi_u16 *pus_len, hi_u8 *puc_param);
38 typedef hi_u32 (*wal_config_set_func)(mac_vap_stru *pst_mac_vap, hi_u16 us_len, const hi_u8 *puc_param);
73 hi_u32 hmac_vap_cfg_priv_stru_size;
74 hi_u32 frw_timeout_stru_size;
75 hi_u32 mac_key_mgmt_stru_size;
76 hi_u32 mac_pmkid_cache_stru_size;
77 hi_u32 mac_curr_rateset_stru_size;
78 hi_u32 hmac_vap_stru_size;
83 hi_u32 reg_info_num;
84 hi_u32 fla
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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/hal/phy/hisiv100/regs/
H A Dhdmi_reg_dphy.c37 hi_s32 hdmi_reg_sscin_bypass_en_set(hi_u32 reg_sscin_bypass_en) in hdmi_reg_sscin_bypass_en_set()
39 hi_u32 *reg_addr = NULL; in hdmi_reg_sscin_bypass_en_set()
42 reg_addr = (hi_u32 *)&(g_hdmi2tx_dphy_regs->ssc_in_set.u32); in hdmi_reg_sscin_bypass_en_set()
50 hi_s32 hdmi_reg_pllfbmash111_en_set(hi_u32 reg_pllfbmash111_en) in hdmi_reg_pllfbmash111_en_set()
52 hi_u32 *reg_addr = NULL; in hdmi_reg_pllfbmash111_en_set()
55 reg_addr = (hi_u32 *)&(g_hdmi2tx_dphy_regs->ssc_in_set.u32); in hdmi_reg_pllfbmash111_en_set()
63 hi_s32 hdmi_reg_dphy_rst_set(hi_u32 reg_rst) in hdmi_reg_dphy_rst_set()
65 hi_u32 *reg_addr = NULL; in hdmi_reg_dphy_rst_set()
68 reg_addr = (hi_u32 *)&(g_hdmi2tx_dphy_regs->dphy_rst.u32); in hdmi_reg_dphy_rst_set()
76 hi_s32 hdmi_reg_aphy_data_clk_height_set(hi_u32 reg_aphy_data_clk_
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/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/include/
H A Dhi_task.h37 hi_u32 id; /* *< Task ID.CNcomment:任务ID CNend */
42 hi_u32 event_stru[3]; /* *< Event: 3 nums.CNcomment:3个事件CNend */
43 hi_u32 event_mask; /* *< Event mask.CNcomment:事件掩码CNend */
44 hi_u32 stack_size; /* *< Task stack size.CNcomment:栈大小CNend */
45 hi_u32 top_of_stack; /* *< Task stack top.CNcomment:栈顶CNend */
46 hi_u32 bottom_of_stack; /* *< Task stack bottom.CNcomment:栈底CNend */
47 hi_u32 mstatus; /* *< Task current mstatus.CNcomment:当前mstatusCNend */
48 hi_u32 mepc; /* *< Task current mepc.CNcomment:当前mepc.CNend */
49 hi_u32 tp; /* *< Task current tp.CNcomment:当前tp.CNend */
50 hi_u32 r
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H A Dhi_isr.h29 hi_u32 r4;
30 hi_u32 r5;
31 hi_u32 r6;
32 hi_u32 r7;
33 hi_u32 r8;
34 hi_u32 r9;
35 hi_u32 r10;
36 hi_u32 r11;
37 hi_u32 pri_mask;
39 hi_u32 s
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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/cbb/vo/vo_dev/arch/hi3516cv500/include/
H A Dvou_drv.h167 hi_u32 layer;
168 hi_u32 frame_wth;
169 hi_u32 frame_hgt;
170 hi_u32 tile_hgt;
171 hi_u32 cmp_ratio;
182 hi_u32 *cmp_size;
184 hi_u32 sti_err_type;
195 hi_u32 layer;
197 hi_u32 cmp_ratio;
201 hi_u32 *cmp_siz
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/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/dma/
H A Ddma.h103 #define dma_pkt_b_to_dma_addr(_virt_addr) ((hi_u32)(_virt_addr) + PKT_B_OFFSET)
104 #define dma_pkt_h_to_dma_addr(_virt_addr) ((hi_u32)(_virt_addr) + PKT_H_OFFSET)
160 hi_u32 channel_0 : 1;
161 hi_u32 channel_1 : 1;
162 hi_u32 channel_2 : 1;
163 hi_u32 channel_3 : 1;
164 hi_u32 reserved : 28;
166 hi_u32 ch_set_u32;
171 hi_u32 dma_en : 1;
172 hi_u32 master1_endiannes
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/device/soc/hisilicon/hi3751v350/sdk_linux/source/msp/drv/include/
H A Dhi_drv_gpioi2c.h25 hi_u32 hi_drv_i2c_get_chip_version(hi_void);
29 hi_s32 hi_drv_gpioi2c_sccb_read(hi_u32 i2c_num, HI_U8 u8_devaddr, HI_U8 u8_reg_address, HI_U8 *pu8_data);
31 hi_s32 hi_drv_gpioi2c_read(hi_u32 i2c_num, HI_U8 u8_devaddr, HI_U8 u8_reg_address, HI_U8 *pu8_data);
32 hi_s32 hi_drv_gpioi2c_write(hi_u32 i2c_num, HI_U8 u8_devaddr, HI_U8 u8_reg_address, HI_U8 u8_data);
33 hi_s32 hi_drv_gpioi2c_create_gpio_i2c(hi_u32 *pu32_i2c_num, hi_u32 scl_gpio_no, hi_u32 sda_gpio_no);
34 hi_s32 hi_drv_gpioi2c_destroy_gpio_i2c(hi_u32 i2c_num);
36 hi_s32 hi_drv_gpioi2c_read_ext(hi_u32 i2c_num, HI_U8 devaddress, hi_u32 addres
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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hifb/drv/hi3516cv500/
H A Dhifb_graphic_hal.h35 hi_void fb_hal_write_reg(hi_u32 *address, hi_u32 value);
39 hi_void hal_sys_set_arb_mode(hi_u32 mode);
40 hi_void hal_sys_set_rd_bus_id(hi_u32 mode);
41 hi_void hal_sys_vdp_reset_clk(hi_u32 sel);
51 hi_bool hal_disp_get_int_state_vcnt(hal_disp_outputchannel chan, hi_u32 *vcnt);
55 hi_bool hal_disp_set_intf_ctrl(hal_disp_intf intf, hi_u32 *ctrl_info);
62 hi_bool hal_disp_set_vt_thd_mode(hal_disp_outputchannel chan, hi_u32 field_mode);
64 hi_bool hal_disp_set_vt_thd(hal_disp_outputchannel chan, hi_u32 vtthd);
66 hi_bool fb_hal_disp_set_int_mask(hi_u32 mask_e
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/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/commonboot/
H A Dboot_rom.h38 hi_void rom_boot_malloc_init(hi_u32 heap_start_addr, hi_u32 heap_end_addr, hi_u32 check_sum);
39 hi_void *rom_boot_malloc(hi_u32 size);
40 hi_u32 rom_boot_free(hi_void *addr);
97 hi_u32 cmd : 8;
98 hi_u32 iftype : 3;
99 hi_u32 dummy : 3;
100 hi_u32 size : 18;
176 #define SFC_BUS_CONFIG1_RD_ENABLE ((hi_u32)
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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/hal/ctrl/hisiv100/regs/
H A Dhdmi_reg_video_path.c39 hi_u32 *reg_addr = NULL; in hdmi_reg_sync_polarity_set()
42 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32); in hdmi_reg_sync_polarity_set()
50 hi_u32 hdmi_reg_sync_polarity_get(hi_void) in hdmi_reg_sync_polarity_get()
52 hi_u32 *reg_addr = NULL; in hdmi_reg_sync_polarity_get()
55 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32); in hdmi_reg_sync_polarity_get()
62 hi_u32 *reg_addr = NULL; in hdmi_reg_timing_sel_set()
65 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32); in hdmi_reg_timing_sel_set()
73 hi_u32 hdmi_reg_timing_sel_get(hi_void) in hdmi_reg_timing_sel_get()
75 hi_u32 *reg_addr = NULL; in hdmi_reg_timing_sel_get()
78 reg_addr = (hi_u32 *) in hdmi_reg_timing_sel_get()
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