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Searched refs:hi_reg_setbit (Results 1 - 10 of 10) sorted by relevance

/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/drivers/flash/
H A Dhi_flashboot_flash.c120 hi_reg_setbit(PMU_CMU_CTL_CMU_CLK_SEL_REG, 8); /* 80M */ in sfc_config_cmu_clk_sel()
123 hi_reg_setbit(PMU_CMU_CTL_CMU_CLK_SEL_REG, 8); /* 48M */ in sfc_config_cmu_clk_sel()
124 hi_reg_setbit(PMU_CMU_CTL_CMU_CLK_SEL_REG, 9); /* 9 */ in sfc_config_cmu_clk_sel()
272 hi_reg_setbit(PMU_CMU_CTL_CMU_CLK_SEL_REG, 8); /* 48M */ in flash_clk_config()
273 hi_reg_setbit(PMU_CMU_CTL_CMU_CLK_SEL_REG, 9); /* 9 */ in flash_clk_config()
277 hi_reg_setbit(PMU_CMU_CTL_CMU_CLK_SEL_REG, 8); /* 8 80M */ in flash_clk_config()
280 hi_reg_setbit(CLDO_CTL_CLK_SEL_REG, 1); in flash_clk_config()
301 hi_reg_setbit(PMU_CMU_CTL_PMU_MAN_CLR_0_REG, 8); /* set 1 left shift 8 */ in flash_clk_config()
302 hi_reg_setbit(CLDO_CTL_CLK_SEL_REG, 0); in flash_clk_config()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/drivers/flash/
H A Dhi_loaderboot_flash.c121 hi_reg_setbit(PMU_CMU_CTL_CMU_CLK_SEL_REG, 8); /* 80M */ in sfc_config_cmu_clk_sel()
124 hi_reg_setbit(PMU_CMU_CTL_CMU_CLK_SEL_REG, 8); /* 48M */ in sfc_config_cmu_clk_sel()
125 hi_reg_setbit(PMU_CMU_CTL_CMU_CLK_SEL_REG, 9); /* 9 */ in sfc_config_cmu_clk_sel()
220 hi_reg_setbit(PMU_CMU_CTL_CMU_CLK_SEL_REG, 8); /* 48M */ in flash_clk_config()
221 hi_reg_setbit(PMU_CMU_CTL_CMU_CLK_SEL_REG, 9); /* 9 */ in flash_clk_config()
225 hi_reg_setbit(PMU_CMU_CTL_CMU_CLK_SEL_REG, 8); /* 8 80M */ in flash_clk_config()
228 hi_reg_setbit(CLDO_CTL_CLK_SEL_REG, 1); in flash_clk_config()
247 hi_reg_setbit(PMU_CMU_CTL_PMU_MAN_CLR_0_REG, 8); /* set 1 left shift 8 */ in flash_clk_config()
248 hi_reg_setbit(CLDO_CTL_CLK_SEL_REG, 0); in flash_clk_config()
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/tsensor/
H A Dhi_tsensor_pm.c88 hi_reg_setbit(W_CTL_UART_MAC80M_CLKEN_REG, TSENSOR_CLK_GATE_BIT); in hi_tsensor_lp_restore()
91 hi_reg_setbit((TSENSOR_BASE_ADDRESS + TSENSOR_MAN_STS), 0); in hi_tsensor_lp_restore()
92 hi_reg_setbit((TSENSOR_BASE_ADDRESS + TSENSOR_AUTO_STS), 0); in hi_tsensor_lp_restore()
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/pwm/
H A Dhi_pwm.c130 hi_reg_setbit(CLDO_CTL_CLK_SEL_REG, 0); in hi_pwm_set_clock()
140 hi_reg_setbit(pwm_en_reg(pwm_base_addr(port)), 0); in pwm_set_enable()
159 hi_reg_setbit(pwm_start_reg(pwm_base_addr(port)), 0); in pwm_take_effect()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/include/
H A Dhi_boot_rom.h87 #define hi_reg_setbit(addr, pos) ((hi_reg_read_val32(addr)) |= ((hi_u32)(1) << (pos))) macro
/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/include/
H A Dhi_types_base.h471 #define hi_reg_setbit(addr, pos) ((hi_reg_read_val32(addr)) |= ((unsigned int)(1) << (pos))) macro
/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H A Dhi_types_base.h470 #define hi_reg_setbit(addr, pos) ((hi_reg_read_val32(addr)) |= ((unsigned int)(1) << (pos))) macro
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/include/
H A Dhi_boot_rom.h87 #define hi_reg_setbit(addr, pos) ((hi_reg_read_val32(addr)) |= ((hi_u32)(1) << (pos))) macro
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/common/
H A Dcmd_loop.c275 hi_reg_setbit(NMI_BASE_ADDRESS + NMI_CTRL, NMI_INT_MOD_DONE_EN_POS); in start_and_wait_update_ver()
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/system/upg/
H A Dupg_common.c768 hi_reg_setbit(UPG_NMI_BASE_ADDRESS + UPG_NMI_CTRL, UPG_NMI_INT_MOD_DONE_EN_POS); in upg_start_and_wait_update_ver()

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