| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk.h | 456 int mux_offset, int mux_shift, int mux_width, int div_shift, int div_width,
500 u8 div_width; member
514 .mux_flags = (mf), .div_shift = (ds), .div_width = (dw), .div_flags = (df), .gate_offset = (go), \
522 .mux_flags = (mf), .div_shift = (ds), .div_width = (dw), .div_flags = (df), .gate_offset = (go), \
530 .mux_flags = (mf), .mux_table = (mt), .div_shift = (ds), .div_width = (dw), .div_flags = (df), \
539 .mux_flags = (_mf), .div_offset = _do, .div_shift = (_ds), .div_width = (_dw), .div_flags = (_df), \
547 .num_parents = 1, .flags = (f), .muxdiv_offset = (mo), .div_shift = (ds), .div_width = (dw), \
554 .num_parents = 1, .flags = (f), .muxdiv_offset = (mo), .div_shift = (ds), .div_width = (dw), \
569 .mux_flags = (mf), .div_shift = (ds), .div_width = (dw), .div_flags = (df), .gate_offset = -1, \
576 .mux_flags = (mf), .div_shift = (ds), .div_width
[all...] |
| H A D | clk.c | 40 u8 div_width, u8 div_flags, struct clk_div_table *div_table, in rockchip_clk_register_branch()
80 if (div_width > 0) { in rockchip_clk_register_branch()
94 div->width = div_width; in rockchip_clk_register_branch()
374 u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, in rockchip_clk_register_composite_brother_branch()
387 mux_flags, mux_table, div_offset, div_shift, div_width, div_flags, div_table, in rockchip_clk_register_composite_brother_branch()
395 brother->mux_width, brother->mux_flags, brother->div_offset, brother->div_shift, brother->div_width, in rockchip_clk_register_composite_brother_branch()
525 list->div_width, list->div_flags, list->div_table, &ctx->lock); in rockchip_clk_register_branches()
528 ctx->reg_base + list->muxdiv_offset, list->div_shift, list->div_width, in rockchip_clk_register_branches()
541 list->mux_flags, list->div_offset, list->div_shift, list->div_width, in rockchip_clk_register_branches()
556 list->div_width, lis in rockchip_clk_register_branches()
37 rockchip_clk_register_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u32 *mux_table, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) rockchip_clk_register_branch() argument
371 rockchip_clk_register_composite_brother_branch( struct rockchip_clk_provider *ctx, const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u32 *mux_table, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, struct rockchip_clk_branch *brother, spinlock_t *lock) rockchip_clk_register_composite_brother_branch() argument
[all...] |
| H A D | clk-ddr.c | 33 int div_width; member
219 int mux_offset, int mux_shift, int mux_width, int div_shift, int div_width, in rockchip_clk_register_ddrclk()
266 ddrclk->div_width = div_width; in rockchip_clk_register_ddrclk()
218 rockchip_clk_register_ddrclk(const char *name, int flags, const char *const *parent_names, u8 num_parents, int mux_offset, int mux_shift, int mux_width, int div_shift, int div_width, int ddr_flag, void __iomem *reg_base) rockchip_clk_register_ddrclk() argument
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| H A D | clk-half-divider.c | 150 u8 mux_flags, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, in rockchip_clk_register_halfdiv()
187 if (div_width > 0) { in rockchip_clk_register_halfdiv()
200 div->width = div_width; in rockchip_clk_register_halfdiv()
148 rockchip_clk_register_halfdiv(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) rockchip_clk_register_halfdiv() argument
|
| /device/soc/rockchip/rk3588/kernel/drivers/soc/rockchip/ |
| H A D | clk.h | 548 int div_shift, int div_width,
596 u8 div_width; member
620 .div_width = dw, \
641 .div_width = dw, \
664 .div_width = dw, \
686 .div_width = dw, \
704 .div_width = dw, \
722 .div_width = dw, \
762 .div_width = dw, \
781 .div_width
[all...] |
| /device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/ |
| H A D | clk.h | 548 int div_shift, int div_width,
596 u8 div_width; member
620 .div_width = dw, \
641 .div_width = dw, \
664 .div_width = dw, \
686 .div_width = dw, \
704 .div_width = dw, \
722 .div_width = dw, \
762 .div_width = dw, \
781 .div_width
[all...] |
| H A D | clk-dclk-divider.c | 98 u8 div_width, u8 div_flags, in rockchip_clk_register_dclk_branch()
139 if (div_width > 0) { in rockchip_clk_register_dclk_branch()
150 div->width = div_width; in rockchip_clk_register_dclk_branch()
91 rockchip_clk_register_dclk_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, unsigned long max_prate, spinlock_t *lock) rockchip_clk_register_dclk_branch() argument
|
| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-dclk-divider.c | 94 u8 mux_flags, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, in rockchip_clk_register_dclk_branch()
132 if (div_width > 0) { in rockchip_clk_register_dclk_branch()
145 div->width = div_width; in rockchip_clk_register_dclk_branch()
92 rockchip_clk_register_dclk_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, unsigned long max_prate, spinlock_t *lock) rockchip_clk_register_dclk_branch() argument
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| /device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop2_clk.c | 49 .num_parents = 1, .flags = (f), .div_width = (w), \
59 u8 div_width; member
276 vop2_clk->div.width = branch->div_width; in vop2_clk_register()
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| /device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop2_clk.c | 60 .div_width = w, \
70 u8 div_width; member
292 vop2_clk->div.width = branch->div_width; in vop2_clk_register()
|