| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | Makefile | 12 clk-vendor-y += clk-dclk-divider.o
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| /device/soc/rockchip/rk3566/vendor/drivers/clk/ |
| H A D | Makefile | 12 clk-vendor-y += clk-dclk-divider.o
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| /device/soc/rockchip/common/vendor/drivers/gpu/drm/rockchip/ebc-dev/tcon/ |
| H A D | ebc_tcon.h | 30 struct clk *dclk; member
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| /device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_drm_vop2.c | 491 struct clk *dclk; member
3284 ret = clk_prepare_enable(vp->dclk); in vop2_initial()
3286 DRM_DEV_ERROR(vop2->dev, "failed to enable dclk for video port%d - %d\n", in vop2_initial()
3308 clk_disable_unprepare(vp->dclk); in vop2_disable()
4908 clock = clk_round_rate(vp->dclk, request_clock * 1000) / 1000; in vop2_crtc_mode_valid()
5141 adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk, in vop2_crtc_mode_fixup()
5273 crtc_clock != clk_get_rate(vp->dclk)) in vop2_crtc_mode_update()
5340 snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id); in vop2_set_dsc_clk()
5391 struct vop2_clk *dclk_core, *dclk_out, *dclk; in vop2_calc_if_clk() local
5474 * HDMI use 1:1 dclk fo in vop2_calc_if_clk()
5882 struct vop2_clk *dclk, *dclk_out, *dclk_core; vop2_crtc_atomic_enable() local
[all...] |
| /device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_drm_vop.c | 267 /* vop dclk */
268 struct clk *dclk; member
274 /* vop dclk reset */
1486 ret = clk_prepare_enable(vop->dclk); in vop_power_enable()
1488 dev_err(vop->dev, "failed to enable dclk - %d\n", ret); in vop_power_enable()
1521 clk_disable_unprepare(vop->dclk); in vop_power_enable()
1600 clk_disable_unprepare(vop->dclk); in vop_crtc_atomic_disable()
2557 clock = clk_round_rate(vop->dclk, request_clock * 0x3e8) / 0x3e8; in vop_crtc_mode_valid()
2838 adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vop->dclk, adj_mode->crtc_clock * 0x3e8), 0x3e8); in vop_crtc_mode_fixup()
2958 crtc_clock != clk_get_rate(vop->dclk)) { in vop_crtc_mode_update()
[all...] |
| H A D | rockchip_drm_vop2.c | 472 struct clk *dclk; member
3279 ret = clk_prepare_enable(vp->dclk); in vop2_initial()
3281 DRM_DEV_ERROR(vop2->dev, "failed to enable dclk for video port%d - %d\n", vp->id, ret); in vop2_initial()
3304 clk_disable_unprepare(vp->dclk); in vop2_disable()
4895 clock = clk_round_rate(vp->dclk, request_clock * 0x3e8) / 0x3e8; in vop2_crtc_mode_valid()
5125 adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk, adj_mode->crtc_clock * 0x3e8), 0x3e8); in vop2_crtc_mode_fixup()
5248 crtc_clock != clk_get_rate(vp->dclk)) { in vop2_crtc_mode_update()
5309 ret = snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id); in vop2_set_dsc_clk()
5821 struct vop2_clk *dclk, *dclk_out, *dclk_core; in vop2_crtc_atomic_enable() local
5830 DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d for vp%d dclk in vop2_crtc_atomic_enable()
[all...] |
| /device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-samsung-hdptx-hdmi.c | 711 struct clk *dclk; member
1997 hdptx->dclk = devm_clk_register(dev, &hdptx->hw); in rockchip_hdptx_phy_clk_register()
1998 if (IS_ERR(hdptx->dclk)) { in rockchip_hdptx_phy_clk_register()
1999 ret = PTR_ERR(hdptx->dclk); in rockchip_hdptx_phy_clk_register()
2004 ret = of_clk_add_provider(np, of_clk_src_simple_get, hdptx->dclk); in rockchip_hdptx_phy_clk_register()
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| /device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/drv/ |
| H A D | ddr_training_impl.c | 3028 unsigned int ac_phy_ctl, dramclk, dclk; in ddr_ac_set_clk() local
3029 dclk = val & PHY_ACPHY_DCLK_MASK; in ddr_ac_set_clk()
3044 ac_phy_ctl |= (dclk << PHY_ACPHY_DCLK0_BIT); /* set cp1p_dclk0 */ in ddr_ac_set_clk()
3045 ac_phy_ctl |= (dclk << PHY_ACPHY_DCLK1_BIT); /* set cp2p_dclk1 */ in ddr_ac_set_clk()
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| /device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/ |
| H A D | ddr_training_impl.c | 3030 unsigned int ac_phy_ctl, dramclk, dclk; in ddr_ac_set_clk() local
3031 dclk = val & PHY_ACPHY_DCLK_MASK; in ddr_ac_set_clk()
3046 ac_phy_ctl |= (dclk << PHY_ACPHY_DCLK0_BIT); /* set cp1p_dclk0 */ in ddr_ac_set_clk()
3047 ac_phy_ctl |= (dclk << PHY_ACPHY_DCLK1_BIT); /* set cp2p_dclk1 */ in ddr_ac_set_clk()
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