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Searched refs:cycle (Results 1 - 13 of 13) sorted by relevance

/device/soc/rockchip/common/sdk_linux/include/soc/rockchip/
H A Dscpi.h48 int scpi_thermal_set_clk_cycle(u32 cycle);
140 static inline int scpi_thermal_set_clk_cycle(u32 cycle) in scpi_thermal_set_clk_cycle() argument
/device/soc/rockchip/rk3588/kernel/include/soc/rockchip/
H A Dscpi.h49 int scpi_thermal_set_clk_cycle(u32 cycle);
142 static inline int scpi_thermal_set_clk_cycle(u32 cycle) in scpi_thermal_set_clk_cycle() argument
/device/soc/rockchip/rk2206/hardware/include/lz_hardware/
H A Dpwm.h91 * @brief Starts PWM signal output from a specified port based on the given output frequency and duty cycle.
96 * @param duty Indicates the duty cycle for PWM signal output. The value ranges from 1 to 99.
97 * @param cycle Indicates the cycle for PWM signal output.
101 unsigned int LzPwmStart(unsigned int port, unsigned int duty, unsigned int cycle);
/device/soc/hisilicon/hi3516dv300/sdk_linux/sample/platform/higv/include/
H A Dhi_gv_listbox.h65 HI_BOOL Cyc; /* Is cycle */
345 * brief Set the focus whether cycle.
349 * param[in] cycle Focus cycle.
353 HI_S32 HI_GV_List_SetCyc(HIGV_HANDLE listHandle, HI_BOOL cycle);
/device/soc/hisilicon/common/platform/mmc/himci_v200/
H A Dhimci.c745 uint32_t cycle, busy; in HimciWaitCardComplete() local
749 for (cycle = 0; cycle < HIMCI_MAX_RETRY_COUNT; cycle++) { in HimciWaitCardComplete()
/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/cif/
H A Ddev.h424 unsigned long cycle; member
H A Dcapture.c5724 unsigned int cycle = 0; in rkcif_monitor_reset_event() local
5766 cycle = fps * timer->frm_num_of_monitor_cycle; in rkcif_monitor_reset_event()
5767 timer->cycle = msecs_to_jiffies(cycle); in rkcif_monitor_reset_event()
5781 timer->timer.expires = jiffies + timer->cycle; in rkcif_monitor_reset_event()
5786 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s:mode:%d, raw height:%d,vblank:%d, cycle:%ld, fps:%llu\n", __func__, in rkcif_monitor_reset_event()
5787 timer->monitor_mode, raw_rect->height, vblank, timer->cycle, div_u64(1000, fps)); in rkcif_monitor_reset_event()
6427 timer->cycle = msecs_to_jiffies(fps); in rkcif_is_reduced_frame_rate()
6428 timer->timer.expires = jiffies + timer->cycle; in rkcif_is_reduced_frame_rate()
6534 mod_timer(&timer->timer, jiffies + timer->cycle); in rkcif_reset_watchdog_timer_handler()
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/cif/
H A Ddev.h383 unsigned long cycle; member
H A Dcapture.c5938 unsigned int cycle = 0; in rkcif_monitor_reset_event() local
5979 cycle = fps * timer->frm_num_of_monitor_cycle; in rkcif_monitor_reset_event()
5980 timer->cycle = msecs_to_jiffies(cycle); in rkcif_monitor_reset_event()
5994 timer->timer.expires = jiffies + timer->cycle; in rkcif_monitor_reset_event()
6000 "%s:mode:%d, raw height:%d,vblank:%d, cycle:%ld, fps:%llu\n", in rkcif_monitor_reset_event()
6002 vblank, timer->cycle, div_u64(1000, fps)); in rkcif_monitor_reset_event()
6690 timer->cycle = msecs_to_jiffies(fps); in rkcif_is_reduced_frame_rate()
6691 timer->timer.expires = jiffies + timer->cycle; in rkcif_is_reduced_frame_rate()
6807 mod_timer(&timer->timer, jiffies + timer->cycle); in rkcif_reset_watchdog_timer_handler()
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
H A Ddw-mipi-dsi-rockchip.c42 #define PHY_STOP_WAIT_TIME(cycle) (((cycle)&0xff) << 8)
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-mipi-dsi.c183 #define PHY_STOP_WAIT_TIME(cycle) (((cycle)&0xff) << 8)
/device/soc/hisilicon/common/hal/middleware/ffmpeg_adapt/
H A Dconfigure_llvm7264 # within a set of N items, N expansions are enough to expose a cycle.
7274 eval is_in $1 \$${1}_deps && die "Dependency cycle at ${1}_deps"
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H A Dwlioctl.h17115 uint16 cycle; member
17761 uint8 duty_cycle_min; /* min duty cycle for TWT(Percentage) */
17948 uint8 dc_max; /* Max supported duty cycle for single TWT */
17949 uint8 resp_type; /* Resp. type(Alt/dict) if duty cycle>max duty cycle */
20164 #define OMI_ULMU_DISABLED_TX_DUTY_CYCLE 0x100u /* Disabled due to tx duty cycle */
20740 uint32 nr_duty_cycle; /* NR duty cycle since last read */

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