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Searched refs:custom (Results 1 - 15 of 15) sorted by relevance

/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/drv/
H A Dddr_training_custom.c44 reg->custom.ive_ddrt_mst_sel = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_cmd_site_save()
45 ddr_write(reg->custom.ive_ddrt_mst_sel & 0xffffffdf, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_cmd_site_save()
48 reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
50 ddr_write(reg->custom.ddrt_clk_reg | (1U << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
56 reg->custom.phy0_age_compst_en = ddr_read(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_cmd_site_save()
57 ddr_write((reg->custom.phy0_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_cmd_site_save()
59 reg->custom.phy1_age_compst_en = ddr_read(DDR_REG_BASE_PHY1 + DDR_PHY_PHYRSCTRL); in ddr_cmd_site_save()
60 ddr_write((reg->custom.phy1_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY1 + DDR_PHY_PHYRSCTRL); in ddr_cmd_site_save()
71 ddr_write(reg->custom.ive_ddrt_mst_sel, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_cmd_site_restore()
74 ddr_write(reg->custom in ddr_cmd_site_restore()
[all...]
H A Dddr_training_impl.h248 struct tr_custom_reg custom; member
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/
H A Dddr_training_custom.c71 relate_reg->custom.phy0_age_compst_en = ddr_read(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_training_save_reg_custom()
72 ddr_write((relate_reg->custom.phy0_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_training_save_reg_custom()
74 relate_reg->custom.phy1_age_compst_en = ddr_read(DDR_REG_BASE_PHY1 + DDR_PHY_PHYRSCTRL); in ddr_training_save_reg_custom()
75 ddr_write((relate_reg->custom.phy1_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY1 + DDR_PHY_PHYRSCTRL); in ddr_training_save_reg_custom()
82 ddr_write(relate_reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_training_restore_reg_custom()
84 ddr_write(relate_reg->custom.phy1_age_compst_en, DDR_REG_BASE_PHY1 + DDR_PHY_PHYRSCTRL); in ddr_training_restore_reg_custom()
H A Dddr_training_impl.h249 struct tr_custom_reg custom; member
/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/boot/hi3518ev300/
H A Dlowlevel_init_v300.c314 reg->custom.ive_ddrt_mst_sel = readl(DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_boot_prepare()
315 writel(reg->custom.ive_ddrt_mst_sel & 0xffffffdf, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_boot_prepare()
318 reg->custom.ddrt_clk_reg = readl(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
320 writel(reg->custom.ddrt_clk_reg | (0x1 << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
326 reg->custom.phy0_age_compst_en = readl(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_prepare()
327 writel((reg->custom.phy0_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_prepare()
329 reg->custom.phy1_age_compst_en = readl(DDR_REG_BASE_PHY1 + DDR_PHY_PHYRSCTRL); in ddr_boot_prepare()
330 writel((reg->custom.phy1_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY1 + DDR_PHY_PHYRSCTRL); in ddr_boot_prepare()
344 writel(reg->custom.ive_ddrt_mst_sel, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_boot_restore()
347 writel(reg->custom in ddr_boot_restore()
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/device/soc/hisilicon/hi3861v100/sdk_liteos/third_party/mbedtls/include/mbedtls/
H A Dctr_drbg.h24 * nonce in the \c custom parameter to mbedtls_ctr_drbg_seed().
227 * calling \p f_entropy and the \p custom string.
234 * strength, then the nonce is taken from \p custom.
236 * you must pass a unique value of \p custom at
244 * you must pass a value of \p custom that is a nonce:
265 * \param custom The personalization string.
279 const unsigned char *custom,
H A Dhmac_drbg.h160 * \param custom The personalization string.
182 const unsigned char *custom,
/device/soc/rockchip/common/sdk_linux/include/media/
H A Dv4l2-async.h61 * @match.custom:
64 * @match.custom.match:
67 * @match.custom.priv:
91 } custom; member
/device/soc/rockchip/common/sdk_linux/include/linux/usb/
H A Dpd_vdo.h31 #define VDO(vid, type, ver, custom) (((vid) << 16) | ((type) << 15) | ((ver) << 13) | ((custom)&0x7FFF))
/device/soc/hisilicon/hi3751v350/sdk_linux/source/msp/drv/
H A DMakefile98 objects += custom
/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/wal/
H A Dwal_customize.c516 oam_error_log0(0, OAM_SF_ANY, "The current custom is only supported nvm file!\n"); in init_ini_param()
570 hi_u32 *custom = (hi_u32 *)data; in init_print_params_proc() local
571 if (custom == HI_NULL) { in init_print_params_proc()
580 (buf_size - string_len - 1), "0X%X\n", custom[cur_pos]); in init_print_params_proc()
583 (buf_size - string_len - 1), "%d\n", custom[cur_pos]); in init_print_params_proc()
1427 oam_error_log0(0, OAM_SF_ANY, "The custom must be config is inited process!\n"); in wal_get_init_value()
/device/soc/rockchip/common/sdk_linux/drivers/media/v4l2-core/
H A Dv4l2-async.c141 if (!asd->match.custom.match) { in match_custom()
146 return asd->match.custom.match(sd->dev, asd); in match_custom()
/device/soc/rockchip/common/sdk_linux/drivers/hid/
H A DMakefile135 obj-$(CONFIG_HID_SENSOR_CUSTOM_SENSOR) += hid-sensor-custom.o
/device/soc/hisilicon/hi3751v350/sdk_linux/
H A Dbase.mak70 HI_BOARD_HEAD_FILE_DIR=${SDK_DIR}/source/custom/${CFG_HI_BOARD_NAME}
/device/soc/hisilicon/common/hal/middleware/ffmpeg_adapt/
H A Dconfigure_llvm414 --custom-allocator=NAME use a supported custom allocator

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