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Searched refs:ctrl (Results 1 - 25 of 107) sorted by relevance

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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/hal/ctrl/hisiv100/regs/
H A Dhdmi_reg_video_path.c133 video_path_ctrl ctrl; in hdmi_reg_video_blank_en_set() local
136 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_video_blank_en_set()
137 ctrl.bits.reg_video_blank_en = reg_video_blank_en; in hdmi_reg_video_blank_en_set()
138 hdmi_tx_reg_write(reg_addr, ctrl.u32); in hdmi_reg_video_blank_en_set()
146 video_path_ctrl ctrl; in hdmi_reg_video_blank_en_get() local
149 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_video_blank_en_get()
150 return ctrl.bits.reg_video_blank_en; in hdmi_reg_video_blank_en_get()
156 video_path_ctrl ctrl; in hdmi_reg_video_lp_disable_set() local
159 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_video_lp_disable_set()
160 ctrl in hdmi_reg_video_lp_disable_set()
169 video_path_ctrl ctrl; hdmi_reg_video_lp_disable_get() local
449 video_dwsm_ctrl ctrl; hdmi_reg_dwsm_vert_bypass_get() local
460 video_dwsm_ctrl ctrl; hdmi_reg_dwsm_vert_en_get() local
472 video_dwsm_ctrl ctrl; hdmi_reg_hori_filter_en_get() local
481 video_dwsm_ctrl ctrl; hdmi_reg_dwsm_hori_en_get() local
492 data_align_ctrl ctrl; hdmi_reg_pxl_div_en_get() local
503 data_align_ctrl ctrl; hdmi_reg_demux_420_en_get() local
514 video_dmux_ctrl ctrl; hdmi_reg_inver_sync_get() local
525 video_dmux_ctrl ctrl; hdmi_reg_vmux_cr_sel_get() local
536 video_dmux_ctrl ctrl; hdmi_reg_vmux_cb_sel_get() local
547 video_dmux_ctrl ctrl; hdmi_reg_vmux_y_sel_get() local
580 multi_csc_ctrl ctrl; hdmi_reg_csc_en_get() local
591 multi_csc_ctrl ctrl; hdmi_reg_csc_mode_get() local
627 multi_csc_ctrl ctrl; hdmi_reg_csc_mode_set() local
640 multi_csc_ctrl ctrl; hdmi_reg_csc_saturate_en_set() local
653 multi_csc_ctrl ctrl; hdmi_reg_csc_en_set() local
666 video_dwsm_ctrl ctrl; hdmi_reg_dwsm_vert_bypass_set() local
679 video_dwsm_ctrl ctrl; hdmi_reg_dwsm_vert_en_set() local
692 video_dwsm_ctrl ctrl; hdmi_reg_hori_filter_en_set() local
705 video_dwsm_ctrl ctrl; hdmi_reg_dwsm_hori_en_set() local
718 data_align_ctrl ctrl; hdmi_reg_pxl_div_en_set() local
731 data_align_ctrl ctrl; hdmi_reg_demux_420_en_set() local
744 video_dmux_ctrl ctrl; hdmi_reg_inver_sync_set() local
757 video_dmux_ctrl ctrl; hdmi_reg_syncmask_en_set() local
770 video_dmux_ctrl ctrl; hdmi_reg_vmux_cr_sel_set() local
783 video_dmux_ctrl ctrl; hdmi_reg_vmux_cb_sel_set() local
796 video_dmux_ctrl ctrl; hdmi_reg_vmux_y_sel_set() local
[all...]
H A Dhdmi_reg_aon.c79 ddc_mst_ctrl ctrl; in hdmi_reg_dcc_man_en_set() local
82 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_dcc_man_en_set()
83 ctrl.bits.dcc_man_en = dcc_man_en; in hdmi_reg_dcc_man_en_set()
84 hdmi_tx_reg_write(reg_addr, ctrl.u32); in hdmi_reg_dcc_man_en_set()
92 ddc_man_ctrl ctrl; in hdmi_reg_ddc_sda_oen_set() local
95 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_ddc_sda_oen_set()
96 ctrl.bits.ddc_sda_oen = ddc_sda_oen; in hdmi_reg_ddc_sda_oen_set()
97 hdmi_tx_reg_write(reg_addr, ctrl.u32); in hdmi_reg_ddc_sda_oen_set()
105 ddc_man_ctrl ctrl; in hdmi_reg_ddc_scl_oen_set() local
108 ctrl in hdmi_reg_ddc_scl_oen_set()
188 ddc_man_ctrl ctrl; hdmi_reg_ddc_sda_st_get() local
198 ddc_man_ctrl ctrl; hdmi_reg_ddc_scl_st_get() local
[all...]
H A Dhdmi_reg_audio_path.c40 tx_audio_ctrl ctrl; in hdmi_reg_aud_spdif_en_set() local
43 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_aud_spdif_en_set()
44 ctrl.bits.aud_spdif_en = aud_spdif_en; in hdmi_reg_aud_spdif_en_set()
45 hdmi_tx_reg_write(reg_addr, ctrl.u32); in hdmi_reg_aud_spdif_en_set()
53 tx_audio_ctrl ctrl; in hdmi_reg_aud_i2s_en_set() local
56 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_aud_i2s_en_set()
57 ctrl.bits.aud_i2s_en = aud_i2s_en; in hdmi_reg_aud_i2s_en_set()
58 hdmi_tx_reg_write(reg_addr, ctrl.u32); in hdmi_reg_aud_i2s_en_set()
66 tx_audio_ctrl ctrl; in hdmi_reg_aud_layout_set() local
69 ctrl in hdmi_reg_aud_layout_set()
79 tx_audio_ctrl ctrl; hdmi_reg_aud_mute_en_set() local
92 tx_audio_ctrl ctrl; hdmi_reg_aud_in_en_set() local
339 tx_audio_ctrl ctrl; hdmi_reg_aud_spdif_en_get() local
349 tx_audio_ctrl ctrl; hdmi_reg_aud_i2s_en_get() local
359 tx_audio_ctrl ctrl; hdmi_reg_aud_layout_get() local
369 tx_audio_ctrl ctrl; hdmi_reg_aud_mute_en_get() local
379 tx_audio_ctrl ctrl; hdmi_reg_aud_in_en_get() local
[all...]
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/
H A Ddrv_hdmi_event.c74 if (tmp_pool->ctrl.pool_id == pool_id) { in event_mach_id()
150 if (tmp_pool->ctrl.pool_id == cur_gid) { in drv_hdmi_event_pool_malloc()
158 if (!tmp_pool->ctrl.pool_id) { in drv_hdmi_event_pool_malloc()
169 (hi_void)memset_s(&tmp_pool->ctrl, sizeof(tmp_pool->ctrl), 0, sizeof(hdmi_event_run_ctrl)); in drv_hdmi_event_pool_malloc()
171 tmp_pool->ctrl.pool_id = cur_gid; in drv_hdmi_event_pool_malloc()
173 *pool_id = tmp_pool->ctrl.pool_id; in drv_hdmi_event_pool_malloc()
175 tmp_pool->ctrl.wakeup_flag = HI_FALSE; in drv_hdmi_event_pool_malloc()
177 tmp_pool->ctrl.event_pool[i] = HDMI_EVENT_BUTT; in drv_hdmi_event_pool_malloc()
199 if (tmp_pool->ctrl in drv_hdmi_event_pool_free()
332 drv_hdmi_event_pool_status_get(hdmi_device_id hdmi_id, hi_u32 pool_num, hdmi_event_run_ctrl *ctrl, hdmi_event_run_cnt *cnt) drv_hdmi_event_pool_status_get() argument
[all...]
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/drivers/core/
H A Ddrv_trng_v200.c32 hisec_com_trng_ctrl ctrl; in drv_trng_randnum() local
40 ctrl.u32 = trng_read(HISEC_COM_TRNG_CTRL); in drv_trng_randnum()
41 if (ctrl.u32 != last) { in drv_trng_randnum()
44 ctrl.bits.mix_enable = 0x00; in drv_trng_randnum()
45 ctrl.bits.drop_enable = 0x00; in drv_trng_randnum()
46 ctrl.bits.pre_process_enable = 0x00; in drv_trng_randnum()
47 ctrl.bits.post_process_enable = 0x00; in drv_trng_randnum()
48 ctrl.bits.post_process_depth = 0x00; in drv_trng_randnum()
49 ctrl.bits.drbg_enable = 0x01; in drv_trng_randnum()
50 ctrl in drv_trng_randnum()
[all...]
H A Ddrv_trng_v100.c36 rng_ctrl ctrl; in drv_trng_randnum() local
44 if (ctrl.u32 != last) { in drv_trng_randnum()
47 ctrl.u32 = trng_read(RNG_CTRL); in drv_trng_randnum()
48 ctrl.bits.filter_enable = 0x00; in drv_trng_randnum()
49 ctrl.bits.mix_en = 0x00; in drv_trng_randnum()
50 ctrl.bits.drop_enable = 0x00; in drv_trng_randnum()
51 ctrl.bits.post_process_enable = 0x01; in drv_trng_randnum()
52 ctrl.bits.post_process_depth = TRNG_POST_PROCESS_DEPTH; in drv_trng_randnum()
53 ctrl.bits.osc_sel = TRNG_OSC_SEL; in drv_trng_randnum()
54 trng_write(RNG_CTRL, ctrl in drv_trng_randnum()
[all...]
H A Ddrv_hash_v100.c114 hash_ctrl ctrl; in drv_hash_cfg_hash_ctrl() local
116 ctrl.u32 = hash_read(REG_CTRL); in drv_hash_cfg_hash_ctrl()
120 ctrl.bits.sha_sel = 0x00; /* SHA1 */ in drv_hash_cfg_hash_ctrl()
122 ctrl.bits.sha_sel = 0x01; /* SHA256 */ in drv_hash_cfg_hash_ctrl()
130 ctrl.bits.read_ctrl = 0; /* 0:read by DMA, 1: read by CPU */ in drv_hash_cfg_hash_ctrl()
131 ctrl.bits.hmac_flag = 0; /* 0:raw hash, 1: hmac */ in drv_hash_cfg_hash_ctrl()
132 ctrl.bits.hardkey_sel = 0; /* 0:cpu key, 1: hard key. */ in drv_hash_cfg_hash_ctrl()
133 ctrl.bits.small_end_en = 1; /* 0:big, 1: little */ in drv_hash_cfg_hash_ctrl()
134 ctrl.bits.sha_init_update_en = 1; /* initial hash value from CPU */ in drv_hash_cfg_hash_ctrl()
136 hash_write(REG_CTRL, ctrl in drv_hash_cfg_hash_ctrl()
[all...]
H A Ddrv_ifep_rsa_v100.c320 sec_rsa_mod_reg ctrl; in drv_rsa_set_width() local
322 ctrl.u32 = 0x00; in drv_rsa_set_width()
323 ctrl.bits.sec_rsa_mod_sel = RSA_MODE_EXP; in drv_rsa_set_width()
324 ctrl.bits.sec_rsa_key_width = width; in drv_rsa_set_width()
325 ifep_rsa_write(REG_SEC_RSA_MOD_REG, ctrl.u32); in drv_rsa_set_width()
326 hi_log_info("REG_SEC_RSA_MOD_REG 0x%x\n", ctrl.u32); in drv_rsa_set_width()
559 sec_rsa_mod_reg ctrl; in drv_rsa_clean_ram() local
561 ctrl.u32 = ifep_rsa_read(REG_SEC_RSA_MOD_REG); in drv_rsa_clean_ram()
562 ctrl.bits.sec_rsa_mod_sel = RSA_MODE_CLEAR_RAM; in drv_rsa_clean_ram()
563 ctrl in drv_rsa_clean_ram()
[all...]
H A Ddrv_symc_v100.c1349 chann_cipher_ctrl ctrl; in drv_symc_cfg() local
1361 ctrl.u32 = symc_read(reg_chann_cipher_ctrl(ctx->hard_chn)); in drv_symc_cfg()
1363 ctrl.bits.decrypt = decrypt; in drv_symc_cfg()
1364 ctrl.bits.mode = ctx->mode; in drv_symc_cfg()
1365 ctrl.bits.alg_sel = ctx->alg; in drv_symc_cfg()
1366 ctrl.bits.width = ctx->width; in drv_symc_cfg()
1367 ctrl.bits.key_length = klen; in drv_symc_cfg()
1368 ctrl.bits.key_sel = ctx->hard_key; in drv_symc_cfg()
1369 ctrl.bits.key_adder = ctx->hard_chn; in drv_symc_cfg()
1370 ctrl in drv_symc_cfg()
1519 chann_cipher_ctrl ctrl; drv_symc_proc_alg() local
1544 chann_cipher_ctrl ctrl; drv_symc_proc_mode() local
1577 chann_cipher_ctrl ctrl; drv_symc_proc_klen() local
1623 chann_cipher_ctrl ctrl; drv_symc_proc_key_src() local
1633 drv_symc_proc_ctrl(symc_chn_status *status, chann_cipher_ctrl ctrl) drv_symc_proc_ctrl() argument
1646 chann_cipher_ctrl ctrl; drv_symc_proc_status() local
[all...]
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/pwm/
H A Dhi_pwm.c35 pwm_ctl *ctrl = HI_NULL; in hi_pwm_init() local
41 ctrl = pwm_get_ctl(port); in hi_pwm_init()
42 if (ctrl->is_init == HI_FALSE) { in hi_pwm_init()
46 ret = hi_sem_bcreate(&(ctrl->pwm_sem), HI_SEM_ONE); in hi_pwm_init()
50 ret = hi_sem_bcreate(&(ctrl->pwm_sem), HI_SEM_ONE); in hi_pwm_init()
54 ret = hi_sem_bcreate(&(ctrl->pwm_sem), HI_SEM_ONE); in hi_pwm_init()
58 ret = hi_sem_bcreate(&(ctrl->pwm_sem), HI_SEM_ONE); in hi_pwm_init()
62 ret = hi_sem_bcreate(&(ctrl->pwm_sem), HI_SEM_ONE); in hi_pwm_init()
66 ret = hi_sem_bcreate(&(ctrl->pwm_sem), HI_SEM_ONE); in hi_pwm_init()
72 ctrl in hi_pwm_init()
103 pwm_ctl *ctrl = HI_NULL; hi_pwm_deinit() local
[all...]
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/compat/
H A Ddrv_klad.c39 klad_ctrl ctrl; in hal_cipher_klad_config() local
48 ctrl.u32 = 0; in hal_cipher_klad_config()
49 ctrl.bits.klad2ci_addr = chn_id; in hal_cipher_klad_config()
50 ctrl.bits.type = target; in hal_cipher_klad_config()
51 ctrl.bits.decrypt = is_decrypt; in hal_cipher_klad_config()
52 ctrl.bits.start = KLAD_CTRL_NOT_START; in hal_cipher_klad_config()
54 (hi_void)hal_cipher_write_reg(KLAD_REG_KLAD_CTRL, ctrl.u32); in hal_cipher_klad_config()
60 klad_ctrl ctrl; in hal_cipher_start_klad() local
62 ctrl.u32 = 0; in hal_cipher_start_klad()
63 hal_cipher_read_reg(KLAD_REG_KLAD_CTRL, &ctrl in hal_cipher_start_klad()
100 klad_ctrl ctrl; hal_cipher_wait_klad_done() local
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/pwm/
H A Dpwm-rockchip.c57 unsigned long ctrl; member
96 val = readl_relaxed(pc->base + pc->data->regs.ctrl); in rockchip_pwm_get_state()
114 u32 ctrl; in rockchip_pwm_config() local
132 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); in rockchip_pwm_config()
135 ctrl |= PWM_ENABLE; in rockchip_pwm_config()
137 ctrl &= ~PWM_ENABLE; in rockchip_pwm_config()
147 ctrl |= (state->oneshot_count - 1) << PWM_ONESHOT_COUNT_SHIFT; in rockchip_pwm_config()
150 ctrl |= PWM_CONTINUOUS; in rockchip_pwm_config()
155 ctrl | in rockchip_pwm_config()
350 u32 enable_conf, ctrl; rockchip_pwm_probe() local
[all...]
/device/soc/hisilicon/common/platform/pwm/
H A Dpwm_hi35xx.h53 volatile uint32_t ctrl; member
61 reg->ctrl &= ~1; in HiPwmDisable()
67 reg->ctrl |= ((1 << PWM_KEEP_OFFSET) | PWM_ENABLE); in HiPwmAlwaysOutput()
77 reg->ctrl &= mask; in HiPwmOutputNumberSquareWaves()
78 reg->ctrl |= PWM_ENABLE; in HiPwmOutputNumberSquareWaves()
86 reg->ctrl &= mask; in HiPwmSetPolarity()
87 reg->ctrl |= (polarity << PWM_INV_OFFSET); in HiPwmSetPolarity()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/secure/
H A Dload_crypto.c96 hi_cipher_kdf_ctrl ctrl; in crypto_prepare() local
115 ctrl.salt = rootkey_iv; in crypto_prepare()
116 ctrl.salt_len = sizeof(rootkey_iv); in crypto_prepare()
117 ctrl.kdf_cnt = KDF_ITERATION_CNT; in crypto_prepare()
118 ctrl.kdf_mode = HI_CIPHER_SSS_KDF_KEY_STORAGE; in crypto_prepare()
119 return hi_cipher_kdf_key_derive(&ctrl); in crypto_prepare()
341 hi_cipher_kdf_ctrl ctrl; in crypto_gen_key_content() local
348 hi_u32 cs = (uintptr_t)(ctrl.key) ^ (hi_u32)sizeof(ctrl.key) ^ (uintptr_t)kdf_key ^ (hi_u32)sizeof(kdf_key); in crypto_gen_key_content()
349 if ((hi_u32)memcpy_s(ctrl in crypto_gen_key_content()
[all...]
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/system/upg/
H A Dkernel_crypto.c112 hi_cipher_kdf_ctrl ctrl; in crypto_prepare() local
129 ctrl.salt = rootkey_iv; in crypto_prepare()
130 ctrl.salt_len = sizeof(rootkey_iv); in crypto_prepare()
131 ctrl.kdf_cnt = ENCRYPT_KDF_ITERATION_CNT; in crypto_prepare()
132 ctrl.kdf_mode = HI_CIPHER_SSS_KDF_KEY_STORAGE; in crypto_prepare()
133 return hi_cipher_kdf_key_derive(&ctrl); in crypto_prepare()
343 hi_cipher_kdf_ctrl ctrl; in crypto_gen_key_content() local
350 if ((hi_u32)memcpy_s(ctrl.key, sizeof(ctrl.key), kdf_key, sizeof(kdf_key)) != EOK) { in crypto_gen_key_content()
353 ctrl in crypto_gen_key_content()
602 hi_cipher_kdf_ctrl ctrl; crypto_upg_file_prepare() local
[all...]
/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/
H A Disp_stats_v3x.c56 u32 value, ctrl; in rkisp_stats_get_rawawb_meas_reg() local
59 ctrl = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_CTRL, id); in rkisp_stats_get_rawawb_meas_reg()
60 if (!(ctrl & ISP3X_3A_MEAS_DONE)) { in rkisp_stats_get_rawawb_meas_reg()
61 v4l2_dbg(1, rkisp_debug, &stats_vdev->dev->v4l2_dev, "%s fail, id:%d ctrl:0x%x\n", __func__, id, ctrl); in rkisp_stats_get_rawawb_meas_reg()
124 isp3_stats_write(stats_vdev, ISP3X_RAWAWB_CTRL, ctrl, id); in rkisp_stats_get_rawawb_meas_reg()
132 u32 i, ctrl; in rkisp_stats_get_rawaf_meas_reg() local
134 ctrl = isp3_stats_read(stats_vdev, ISP3X_RAWAF_CTRL, id); in rkisp_stats_get_rawaf_meas_reg()
135 if (!(ctrl & ISP3X_3A_MEAS_DONE)) { in rkisp_stats_get_rawaf_meas_reg()
136 v4l2_dbg(1, rkisp_debug, &stats_vdev->dev->v4l2_dev, "%s fail, id:%d ctrl in rkisp_stats_get_rawaf_meas_reg()
166 u32 addr, value, ctrl; rkisp_stats_get_rawaebig_meas_reg() local
220 u32 addr, ctrl; rkisp_stats_get_rawhstbig_meas_reg() local
362 u32 value, ctrl; rkisp_stats_get_rawaelite_meas_reg() local
393 u32 ctrl; rkisp_stats_get_rawhstlite_meas_reg() local
521 u32 value, rd_buf_idx, ctrl; rkisp_stats_get_rawawb_meas_ddr() local
591 u32 i, rd_buf_idx, *ddr_addr, ctrl; rkisp_stats_get_rawaf_meas_ddr() local
630 u32 i, value, addr, rd_buf_idx, ctrl; rkisp_stats_get_rawaebig_meas_ddr() local
689 u32 i, rd_buf_idx, *ddr_addr, addr, ctrl; rkisp_stats_get_rawhstbig_meas_ddr() local
836 u32 i, value, rd_buf_idx, *ddr_addr, ctrl; rkisp_stats_get_rawaelite_meas_ddr() local
869 u32 *ddr_addr, rd_buf_idx, i, ctrl; rkisp_stats_get_rawhstlite_meas_ddr() local
[all...]
H A Dbridge_v30.c31 u32 ctrl = CIF_DUAL_CROP_CFG_UPD; in crop_on() local
37 ctrl |= rkisp_read(ispdev, CIF_DUAL_CROP_CTRL, true); in crop_on()
39 ctrl &= ~(CIF_DUAL_CROP_MP_MODE_YUV | CIF_DUAL_CROP_MP_MODE_RAW); in crop_on()
41 ctrl |= CIF_DUAL_CROP_MP_MODE_YUV; in crop_on()
43 rkisp_write(ispdev, CIF_DUAL_CROP_CTRL, ctrl, false); in crop_on()
49 u32 ctrl = CIF_DUAL_CROP_GEN_CFG_UPD; in crop_off() local
51 ctrl = rkisp_read(ispdev, CIF_DUAL_CROP_CTRL, true); in crop_off()
52 ctrl &= ~(CIF_DUAL_CROP_MP_MODE_YUV | CIF_DUAL_CROP_MP_MODE_RAW); in crop_off()
53 rkisp_write(ispdev, CIF_DUAL_CROP_CTRL, ctrl, false); in crop_off()
/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/isp/
H A Disp_stats_v3x.c57 u32 value, ctrl; in rkisp_stats_get_rawawb_meas_reg() local
60 ctrl = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_CTRL, id); in rkisp_stats_get_rawawb_meas_reg()
61 if (!(ctrl & ISP3X_3A_MEAS_DONE)) { in rkisp_stats_get_rawawb_meas_reg()
63 "%s fail, id:%d ctrl:0x%x\n", __func__, id, ctrl); in rkisp_stats_get_rawawb_meas_reg()
135 isp3_stats_write(stats_vdev, ISP3X_RAWAWB_CTRL, ctrl, id); in rkisp_stats_get_rawawb_meas_reg()
144 u32 i, ctrl; in rkisp_stats_get_rawaf_meas_reg() local
146 ctrl = isp3_stats_read(stats_vdev, ISP3X_RAWAF_CTRL, id); in rkisp_stats_get_rawaf_meas_reg()
147 if (!(ctrl & ISP3X_3A_MEAS_DONE)) { in rkisp_stats_get_rawaf_meas_reg()
149 "%s fail, id:%d ctrl in rkisp_stats_get_rawaf_meas_reg()
180 u32 addr, value, ctrl; rkisp_stats_get_rawaebig_meas_reg() local
237 u32 addr, ctrl; rkisp_stats_get_rawhstbig_meas_reg() local
386 u32 value, ctrl; rkisp_stats_get_rawaelite_meas_reg() local
418 u32 ctrl; rkisp_stats_get_rawhstlite_meas_reg() local
547 u32 value, rd_buf_idx, ctrl; rkisp_stats_get_rawawb_meas_ddr() local
631 u32 i, rd_buf_idx, *ddr_addr, ctrl; rkisp_stats_get_rawaf_meas_ddr() local
672 u32 i, value, addr, rd_buf_idx, ctrl; rkisp_stats_get_rawaebig_meas_ddr() local
733 u32 i, rd_buf_idx, *ddr_addr, addr, ctrl; rkisp_stats_get_rawhstbig_meas_ddr() local
886 u32 i, value, rd_buf_idx, *ddr_addr, ctrl; rkisp_stats_get_rawaelite_meas_ddr() local
920 u32 *ddr_addr, rd_buf_idx, i, ctrl; rkisp_stats_get_rawhstlite_meas_ddr() local
[all...]
H A Dbridge_v30.c32 u32 ctrl = CIF_DUAL_CROP_CFG_UPD; in crop_on() local
38 ctrl |= rkisp_read(ispdev, CIF_DUAL_CROP_CTRL, true); in crop_on()
40 ctrl &= ~(CIF_DUAL_CROP_MP_MODE_YUV | CIF_DUAL_CROP_MP_MODE_RAW); in crop_on()
42 ctrl |= CIF_DUAL_CROP_MP_MODE_YUV; in crop_on()
43 rkisp_write(ispdev, CIF_DUAL_CROP_CTRL, ctrl, false); in crop_on()
49 u32 ctrl = CIF_DUAL_CROP_GEN_CFG_UPD; in crop_off() local
51 ctrl = rkisp_read(ispdev, CIF_DUAL_CROP_CTRL, true); in crop_off()
52 ctrl &= ~(CIF_DUAL_CROP_MP_MODE_YUV | CIF_DUAL_CROP_MP_MODE_RAW); in crop_off()
53 rkisp_write(ispdev, CIF_DUAL_CROP_CTRL, ctrl, false); in crop_off()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/secure/
H A Dcrypto.c146 hi_cipher_kdf_ctrl ctrl; in crypto_prepare() local
165 ctrl.salt = rootkey_iv; in crypto_prepare()
166 ctrl.salt_len = sizeof(rootkey_iv); in crypto_prepare()
167 ctrl.kdf_cnt = KDF_ITERATION_CNT; in crypto_prepare()
171 ctrl.kdf_mode = HI_CIPHER_SSS_KDF_KEY_STORAGE; in crypto_prepare()
172 return hi_cipher_kdf_key_derive(&ctrl); in crypto_prepare()
394 hi_cipher_kdf_ctrl ctrl; in crypto_gen_key_content() local
401 hi_u32 cs = (uintptr_t)(ctrl.key) ^ (hi_u32)sizeof(ctrl.key) ^ (uintptr_t)kdf_key ^ (hi_u32)sizeof(kdf_key); in crypto_gen_key_content()
402 if ((hi_u32)memcpy_s(ctrl in crypto_gen_key_content()
834 hi_cipher_kdf_ctrl ctrl; boot_crypto_upg_file_prepare() local
[all...]
/device/qemu/arm_mps3_an547/liteos_m/board/driver/
H A Darm_uart_drv.c26 volatile uint32_t ctrl; /* Offset: 0x008 (R/W) control register */ member
71 p_uart->ctrl = ARM_UART_RX_EN | ARM_UART_TX_EN; in arm_uart_init()
174 p_uart->ctrl |= ARM_UART_TX_INTR_EN; in arm_uart_irq_tx_enable()
185 p_uart->ctrl &= ~ARM_UART_TX_INTR_EN; in arm_uart_irq_tx_disable()
210 p_uart->ctrl |= ARM_UART_RX_INTR_EN; in arm_uart_irq_rx_enable()
221 p_uart->ctrl &= ~ARM_UART_RX_INTR_EN; in arm_uart_irq_rx_disable()
/device/qemu/arm_mps2_an386/liteos_m/board/driver/
H A Darm_uart_drv.c26 volatile uint32_t ctrl; /* Offset: 0x008 (R/W) control register */ member
71 p_uart->ctrl = ARM_UART_RX_EN | ARM_UART_TX_EN; in arm_uart_init()
174 p_uart->ctrl |= ARM_UART_TX_INTR_EN; in arm_uart_irq_tx_enable()
185 p_uart->ctrl &= ~ARM_UART_TX_INTR_EN; in arm_uart_irq_tx_disable()
210 p_uart->ctrl |= ARM_UART_RX_INTR_EN; in arm_uart_irq_rx_enable()
221 p_uart->ctrl &= ~ARM_UART_RX_INTR_EN; in arm_uart_irq_rx_disable()
/device/soc/rockchip/common/sdk_linux/drivers/mmc/core/
H A Dsdio.c229 u8 ctrl; in sdio_enable_wide() local
239 ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_IF, 0, &ctrl); in sdio_enable_wide()
244 if ((ctrl & SDIO_BUS_WIDTH_MASK) == SDIO_BUS_WIDTH_RESERVED) { in sdio_enable_wide()
245 pr_warn("%s: SDIO_CCCR_IF is invalid: 0x%02x\n", mmc_hostname(card->host), ctrl); in sdio_enable_wide()
249 ctrl &= ~SDIO_BUS_WIDTH_MASK; in sdio_enable_wide()
250 ctrl |= SDIO_BUS_WIDTH_4BIT; in sdio_enable_wide()
252 ret = mmc_io_rw_direct(card, 1, 0, SDIO_CCCR_IF, ctrl, NULL); in sdio_enable_wide()
269 u8 ctrl; in sdio_disable_cd() local
275 ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_IF, 0, &ctrl); in sdio_disable_cd()
280 ctrl | in sdio_disable_cd()
292 u8 ctrl; sdio_disable_wide() local
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/pinctrl/
H A Dpinctrl-rockchip.c241 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in pin_to_bank()
252 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in bank_num_to_bank()
255 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { in bank_num_to_bank()
772 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_recalced_mux() local
776 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux()
777 data = &ctrl->iomux_recalced[i]; in rockchip_get_recalced_mux()
783 if (i >= ctrl->niomux_recalced) { in rockchip_get_recalced_mux()
1354 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_mux_route() local
2384 struct rockchip_pin_ctrl *ctrl = info->ctrl; rockchip_get_drive_perpin() local
2461 struct rockchip_pin_ctrl *ctrl = info->ctrl; rockchip_set_drive_perpin() local
2596 struct rockchip_pin_ctrl *ctrl = info->ctrl; rockchip_get_pull() local
2642 struct rockchip_pin_ctrl *ctrl = info->ctrl; rockchip_set_pull() local
2765 struct rockchip_pin_ctrl *ctrl = info->ctrl; rockchip_get_schmitt() local
2795 struct rockchip_pin_ctrl *ctrl = info->ctrl; rockchip_set_schmitt() local
2856 struct rockchip_pin_ctrl *ctrl = info->ctrl; rockchip_get_slew_rate() local
2879 struct rockchip_pin_ctrl *ctrl = info->ctrl; rockchip_set_slew_rate() local
2973 rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, enum pin_config_param pull) rockchip_pinconf_pull_valid() argument
3404 struct rockchip_pin_ctrl *ctrl; rockchip_pinctrl_get_soc_data() local
3609 struct rockchip_pin_ctrl *ctrl; rockchip_pinctrl_probe() local
[all...]
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/drivers/
H A Dkapi_symc.c36 hi_cipher_ctrl ctrl; /* control information */ member
621 if (memcpy_s(ctx->ctrl.iv, AES_IV_SIZE, cfg->iv, cfg->ivlen) != EOK) { in kapi_symc_cpy_key_iv()
633 if (memcpy_s(ctx->ctrl.key, AES_KEY_256BIT, cfg->fkey, set_cfg->klen) != EOK) { in kapi_symc_cpy_key_iv()
681 /* save ctrl */ in kapi_symc_cfg_set_param()
682 (hi_void)memset_s(&ctx->ctrl, sizeof(hi_cipher_ctrl), 0, sizeof(hi_cipher_ctrl)); in kapi_symc_cfg_set_param()
683 ctx->ctrl.key_by_ca = set_cfg->byca; in kapi_symc_cfg_set_param()
684 ctx->ctrl.alg = cfg->alg; in kapi_symc_cfg_set_param()
685 ctx->ctrl.bit_width = cfg->width; in kapi_symc_cfg_set_param()
686 ctx->ctrl.ca_type = set_cfg->ca_type; in kapi_symc_cfg_set_param()
687 ctx->ctrl in kapi_symc_cfg_set_param()
744 kapi_symc_get_cfg(hi_u32 id, hi_cipher_ctrl *ctrl) kapi_symc_get_cfg() argument
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