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/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/include/
H A Dhi_atomic.h33 volatile hi_s32 counter; member
37 #define hi_atomic_read(v) ((v)->counter)
38 #define hi_atomic_set(v, i) (((v)->counter) = (i))
107 v->counter += i; in hi_atomic_add_return()
109 return v->counter; in hi_atomic_add_return()
138 v->counter = v->counter - i; in hi_atomic_sub_return()
141 return v->counter; in hi_atomic_sub_return()
209 v->counter += i; in hi_atomic_add_return_optimize()
211 return v->counter; in hi_atomic_add_return_optimize()
[all...]
/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H A Dhi_atomic.h34 volatile hi_s32 counter; member
38 #define hi_atomic_read(v) ((v)->counter)
39 #define hi_atomic_set(v, i) (((v)->counter) = (i))
95 v->counter += i; in hi_atomic_add_return()
97 return v->counter; in hi_atomic_add_return()
122 v->counter = v->counter - i; in hi_atomic_sub_return()
125 return v->counter; in hi_atomic_sub_return()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/common/
H A Dmali_spinlock_reentrant.c37 MALI_DEBUG_ASSERT(0 == spinlock->counter && 0 == spinlock->owner); in mali_spinlock_reentrant_term()
56 MALI_DEBUG_ASSERT(0 == spinlock->owner && 0 == spinlock->counter); in mali_spinlock_reentrant_wait()
62 ++spinlock->counter; in mali_spinlock_reentrant_wait()
71 --spinlock->counter; in mali_spinlock_reentrant_signal()
72 if (0 == spinlock->counter) { in mali_spinlock_reentrant_signal()
H A Dmali_pp_job.c24 static u32 pp_counter_src0 = MALI_HW_CORE_NO_COUNTER; /**< Performance counter 0, MALI_HW_CORE_NO_COUNTER for disabled */
25 static u32 pp_counter_src1 = MALI_HW_CORE_NO_COUNTER; /**< Performance counter 1, MALI_HW_CORE_NO_COUNTER for disabled */
75 /* These counters apply for all virtual jobs, and where no per sub job counter is specified */ in mali_pp_job_create()
79 /* We only copy the per sub job array if it is enabled with at least one counter */ in mali_pp_job_create()
217 /* Virtual jobs always use the global job counter (or if there are per sub job counters at all) */ in mali_pp_job_get_perf_counter_src0()
222 /* Use per sub job counter if enabled... */ in mali_pp_job_get_perf_counter_src0()
227 /* ...else default to global job counter */ in mali_pp_job_get_perf_counter_src0()
233 /* Virtual jobs always use the global job counter (or if there are per sub job counters at all) */ in mali_pp_job_get_perf_counter_src1()
235 /* Virtual jobs always use the global job counter */ in mali_pp_job_get_perf_counter_src1()
239 /* Use per sub job counter i in mali_pp_job_get_perf_counter_src1()
248 mali_pp_job_set_pp_counter_global_src0(u32 counter) mali_pp_job_set_pp_counter_global_src0() argument
253 mali_pp_job_set_pp_counter_global_src1(u32 counter) mali_pp_job_set_pp_counter_global_src1() argument
258 mali_pp_job_set_pp_counter_sub_job_src0(u32 sub_job, u32 counter) mali_pp_job_set_pp_counter_sub_job_src0() argument
277 mali_pp_job_set_pp_counter_sub_job_src1(u32 sub_job, u32 counter) mali_pp_job_set_pp_counter_sub_job_src1() argument
[all...]
H A Dmali_spinlock_reentrant.h23 u32 counter; member
67 return (tid == spinlock->owner && 0 < spinlock->counter); in mali_spinlock_reentrant_is_held()
H A Dmali_l2_cache.c149 MALI_PRINT_ERROR(("Mali L2 cache: Failed to create counter lock for L2 cache core %s\n", in mali_l2_cache_create()
229 * set set the counter value to zero as well. in mali_l2_cache_power_down()
255 struct mali_l2_cache_core *cache, u32 source_id, u32 counter) in mali_l2_cache_core_set_counter_src()
268 cache->counter_src0 = counter; in mali_l2_cache_core_set_counter_src()
274 cache->counter_src1 = counter; in mali_l2_cache_core_set_counter_src()
282 if (MALI_HW_CORE_NO_COUNTER != counter) { in mali_l2_cache_core_set_counter_src()
283 hw_src = counter; in mali_l2_cache_core_set_counter_src()
288 /* Set counter src */ in mali_l2_cache_core_set_counter_src()
254 mali_l2_cache_core_set_counter_src( struct mali_l2_cache_core *cache, u32 source_id, u32 counter) mali_l2_cache_core_set_counter_src() argument
H A Dmali_gp_job.c18 static u32 gp_counter_src0 = MALI_HW_CORE_NO_COUNTER; /**< Performance counter 0, MALI_HW_CORE_NO_COUNTER for disabled */
19 static u32 gp_counter_src1 = MALI_HW_CORE_NO_COUNTER; /**< Performance counter 1, MALI_HW_CORE_NO_COUNTER for disabled */
279 void mali_gp_job_set_gp_counter_src0(u32 counter) in mali_gp_job_set_gp_counter_src0() argument
281 gp_counter_src0 = counter; in mali_gp_job_set_gp_counter_src0()
289 void mali_gp_job_set_gp_counter_src1(u32 counter) in mali_gp_job_set_gp_counter_src1() argument
291 gp_counter_src1 = counter; in mali_gp_job_set_gp_counter_src1()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/common/
H A Dmali_spinlock_reentrant.c38 MALI_DEBUG_ASSERT(spinlock->counter == 0 && spinlock->owner == 0); in mali_spinlock_reentrant_term()
57 MALI_DEBUG_ASSERT(spinlock->owner == 0 && spinlock->counter == 0); in mali_spinlock_reentrant_wait()
63 ++spinlock->counter; in mali_spinlock_reentrant_wait()
72 --spinlock->counter; in mali_spinlock_reentrant_signal()
73 if (spinlock->counter == 0) { in mali_spinlock_reentrant_signal()
H A Dmali_pp_job.c26 MALI_HW_CORE_NO_COUNTER; /**< Performance counter 0, MALI_HW_CORE_NO_COUNTER for disabled */
28 MALI_HW_CORE_NO_COUNTER; /**< Performance counter 1, MALI_HW_CORE_NO_COUNTER for disabled */
85 /* These counters apply for all virtual jobs, and where no per sub job counter is specified */ in mali_pp_job_create()
89 /* We only copy the per sub job array if it is enabled with at least one counter */ in mali_pp_job_create()
225 /* Virtual jobs always use the global job counter (or if there are per sub job counters at all) */ in mali_pp_job_get_perf_counter_src0()
230 /* Use per sub job counter if enabled... */ in mali_pp_job_get_perf_counter_src0()
235 /* ...else default to global job counter */ in mali_pp_job_get_perf_counter_src0()
241 /* Virtual jobs always use the global job counter (or if there are per sub job counters at all) */ in mali_pp_job_get_perf_counter_src1()
243 /* Virtual jobs always use the global job counter */ in mali_pp_job_get_perf_counter_src1()
247 /* Use per sub job counter i in mali_pp_job_get_perf_counter_src1()
256 mali_pp_job_set_pp_counter_global_src0(u32 counter) mali_pp_job_set_pp_counter_global_src0() argument
261 mali_pp_job_set_pp_counter_global_src1(u32 counter) mali_pp_job_set_pp_counter_global_src1() argument
266 mali_pp_job_set_pp_counter_sub_job_src0(u32 sub_job, u32 counter) mali_pp_job_set_pp_counter_sub_job_src0() argument
285 mali_pp_job_set_pp_counter_sub_job_src1(u32 sub_job, u32 counter) mali_pp_job_set_pp_counter_sub_job_src1() argument
[all...]
H A Dmali_spinlock_reentrant.h24 u32 counter; member
68 return (tid == spinlock->owner && 0 < spinlock->counter); in mali_spinlock_reentrant_is_held()
H A Dmali_l2_cache.c139 ("Mali L2 cache: Failed to create counter lock for L2 cache core %s\n", cache->hw_core.description)); in mali_l2_cache_create()
218 * set set the counter value to zero as well. in mali_l2_cache_power_down()
238 void mali_l2_cache_core_set_counter_src(struct mali_l2_cache_core *cache, u32 source_id, u32 counter) in mali_l2_cache_core_set_counter_src() argument
251 cache->counter_src0 = counter; in mali_l2_cache_core_set_counter_src()
257 cache->counter_src1 = counter; in mali_l2_cache_core_set_counter_src()
265 if (MALI_HW_CORE_NO_COUNTER != counter) { in mali_l2_cache_core_set_counter_src()
266 hw_src = counter; in mali_l2_cache_core_set_counter_src()
271 /* Set counter src */ in mali_l2_cache_core_set_counter_src()
H A Dmali_gp_job.c20 MALI_HW_CORE_NO_COUNTER; /**< Performance counter 0, MALI_HW_CORE_NO_COUNTER for disabled */
22 MALI_HW_CORE_NO_COUNTER; /**< Performance counter 1, MALI_HW_CORE_NO_COUNTER for disabled */
285 void mali_gp_job_set_gp_counter_src0(u32 counter) in mali_gp_job_set_gp_counter_src0() argument
287 gp_counter_src0 = counter; in mali_gp_job_set_gp_counter_src0()
295 void mali_gp_job_set_gp_counter_src1(u32 counter) in mali_gp_job_set_gp_counter_src1() argument
297 gp_counter_src1 = counter; in mali_gp_job_set_gp_counter_src1()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/ipa/backend/
H A Dmali_kbase_ipa_counter_common_csf.c28 * instead, to avoid extrapolating small amounts of counter data across
39 /* Maximum increment that is expected for a counter value during a sampling
44 * - max increment of 4 in per core counter value at every clock cycle.
47 * If a counter increases by an amount greater than this value, then an error
76 * @model_data: Pointer to counter model data
78 * Register IPA counter model as a client of kbase_ipa_control, which
93 /* Value for GPU_ACTIVE counter also needs to be queried. It is required in kbase_ipa_attach_ipa_control()
108 /* Fill in the description for GPU_ACTIVE counter which is always in kbase_ipa_attach_ipa_control()
119 const struct kbase_ipa_counter *counter = in kbase_ipa_attach_ipa_control() local
122 perf_counters[cnt_idx].type = counter in kbase_ipa_attach_ipa_control()
130 const struct kbase_ipa_counter *counter = kbase_ipa_attach_ipa_control() local
393 const struct kbase_ipa_counter *counter = kbase_ipa_counter_common_model_init() local
407 const struct kbase_ipa_counter *counter = kbase_ipa_counter_common_model_init() local
[all...]
H A Dmali_kbase_ipa_counter_jm.c31 /* Performance counter blocks base offsets */
36 /* JM counter block offsets */
39 /* Tiler counter block offsets */
42 /* MEMSYS counter block offsets */
45 /* SC counter block offsets */
62 * get_jm_counter() - get performance counter offset inside the Job Manager block
64 * @counter_block_offset: offset in bytes of the performance counter inside the Job Manager block.
66 * Return: Block offset in bytes of the required performance counter.
75 * get_memsys_counter() - get performance counter offset inside the Memory System block
77 * @counter_block_offset: offset in bytes of the performance counter insid
125 u32 counter; kbase_g7x_sum_all_memsys_blocks() local
144 u32 counter; kbase_g7x_sum_all_shader_cores() local
164 u32 counter; kbase_g7x_jm_single_counter() local
181 u32 counter = kbase_g7x_power_model_get_jm_counter(model_data, JM_GPU_ACTIVE); kbase_g7x_get_active_cycles() local
[all...]
H A Dmali_kbase_ipa_counter_common_jm.h32 /* Number of bytes per hardware counter in a vinstr_buffer. */
54 * counter sample period
55 * @hvirt_cli: hardware counter virtualizer client handle
64 * @min_sample_cycles: If the value of the GPU_ACTIVE counter (the number of
66 * min_sample_cycles, the counter model will return an
70 * counter dump.
91 * @op: which operation to be performed on the counter values
92 * @counter_block_offset: block offset in bytes of the counter used to calculate energy for IPA group
102 * kbase_ipa_sum_all_shader_cores() - sum a counter over all cores
106 * @counter
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H A Dmali_kbase_ipa_counter_common_jm.c28 * instead, to avoid extrapolating small amounts of counter data across
34 * read_hwcnt() - read a counter value
38 * Return: A 32-bit counter value. Range: 0 < value < 2^27 (worst case would be
68 s32 coeff, u32 counter) in kbase_ipa_sum_all_shader_cores()
80 base + counter); in kbase_ipa_sum_all_shader_cores()
95 s32 coeff, u32 counter) in kbase_ipa_sum_all_memsys_blocks()
106 base + counter); in kbase_ipa_sum_all_memsys_blocks()
119 s32 coeff, u32 counter) in kbase_ipa_single_counter()
122 const u32 counter_value = kbase_ipa_read_hwcnt(model_data, counter); in kbase_ipa_single_counter()
148 /* Disable cycle counter onl in kbase_ipa_attach_vinstr()
66 kbase_ipa_sum_all_shader_cores( struct kbase_ipa_model_vinstr_data *model_data, s32 coeff, u32 counter) kbase_ipa_sum_all_shader_cores() argument
93 kbase_ipa_sum_all_memsys_blocks( struct kbase_ipa_model_vinstr_data *model_data, s32 coeff, u32 counter) kbase_ipa_sum_all_memsys_blocks() argument
117 kbase_ipa_single_counter( struct kbase_ipa_model_vinstr_data *model_data, s32 coeff, u32 counter) kbase_ipa_single_counter() argument
[all...]
/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/oal/
H A Doal_atomic.h51 volatile int counter; member
125 : "r"(&v->counter), "Ir"(i) in atomic_add()
143 : "r"(&v->counter), "Ir"(i) in atomic_add_return()
163 : "r"(&v->counter), "Ir"(i) in atomic_sub()
181 : "r"(&v->counter), "Ir"(i) in atomic_sub_return()
201 val = v->counter; in oal_atomic_add_return()
202 v->counter = val += i; in oal_atomic_add_return()
215 val = v->counter; in oal_atomic_sub_return()
216 v->counter = val -= i; in oal_atomic_sub_return()
315 return p_vector->counter; in oal_atomic_read()
[all...]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/ipa/
H A Dmali_kbase_ipa_vinstr_g7x.c27 /* Performance counter blocks base offsets */
32 /* JM counter block offsets */
35 /* Tiler counter block offsets */
38 /* MEMSYS counter block offsets */
41 /* SC counter block offsets */
58 * get_jm_counter() - get performance counter offset inside the Job Manager block
60 * @counter_block_offset: offset in bytes of the performance counter inside the Job Manager block.
62 * Return: Block offset in bytes of the required performance counter.
71 * get_memsys_counter() - get performance counter offset inside the Memory System block
73 * @counter_block_offset: offset in bytes of the performance counter insid
112 u32 counter; kbase_g7x_sum_all_memsys_blocks() local
129 u32 counter; kbase_g7x_sum_all_shader_cores() local
146 u32 counter; kbase_g7x_jm_single_counter() local
161 u32 counter = kbase_g7x_power_model_get_jm_counter(model_data, JM_GPU_ACTIVE); kbase_g7x_get_active_cycles() local
[all...]
H A Dmali_kbase_ipa_vinstr_common.h33 /* Number of bytes per hardware counter in a vinstr_buffer. */
52 * counter sample period
53 * @hvirt_cli: hardware counter virtualizer client handle
62 * @min_sample_cycles: If the value of the GPU_ACTIVE counter (the number of
64 * min_sample_cycles, the counter model will return an
68 * counter dump.
89 * @op: which operation to be performed on the counter values
90 * @counter_block_offset: block offset in bytes of the counter used to calculate energy for IPA group
100 * kbase_ipa_sum_all_shader_cores() - sum a counter over all cores
104 * @counter offse
[all...]
H A Dmali_kbase_ipa_vinstr_common.c29 * instead, to avoid extrapolating small amounts of counter data across
35 * read_hwcnt() - read a counter value
39 * Return: A 32-bit counter value. Range: 0 < value < 2^27 (worst case would be
65 s64 kbase_ipa_sum_all_shader_cores(struct kbase_ipa_model_vinstr_data *model_data, s32 coeff, u32 counter) in kbase_ipa_sum_all_shader_cores() argument
76 u32 counter_value = kbase_ipa_read_hwcnt(model_data, base + counter); in kbase_ipa_sum_all_shader_cores()
89 s64 kbase_ipa_sum_all_memsys_blocks(struct kbase_ipa_model_vinstr_data *model_data, s32 coeff, u32 counter) in kbase_ipa_sum_all_memsys_blocks() argument
99 u32 counter_value = kbase_ipa_read_hwcnt(model_data, base + counter); in kbase_ipa_sum_all_memsys_blocks()
110 s64 kbase_ipa_single_counter(struct kbase_ipa_model_vinstr_data *model_data, s32 coeff, u32 counter) in kbase_ipa_single_counter() argument
113 const u32 counter_value = kbase_ipa_read_hwcnt(model_data, counter); in kbase_ipa_single_counter()
139 /* Disable cycle counter onl in kbase_ipa_attach_vinstr()
[all...]
/device/soc/rockchip/common/vendor/drivers/devfreq/event/
H A Drockchip-nocp.c81 u32 counter = 0, counter0 = 0, counter1 = 0; in rockchip_nocp_get_event() local
88 counter = (counter0 & 0xffff) | ((counter1 & 0xffff) << 0x10); in rockchip_nocp_get_event()
89 counter = counter / 0xf4240; in rockchip_nocp_get_event()
91 edata->load_count = (counter * 0x3e8) / time_ms; in rockchip_nocp_get_event()
/device/soc/hisilicon/hi3861v100/sdk_liteos/third_party/mbedtls/include/mbedtls/
H A Dchacha20.h121 * \brief This function sets the nonce and initial counter value.
133 * \param counter The initial counter value. This is usually \c 0.
141 uint32_t counter );
194 * \param counter The initial counter value. This is usually \c 0.
207 uint32_t counter,
/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/mac/hmac/
H A Dhmac_wapi_wpi.c61 hi_u32 counter; in hmac_wpi_encrypt() local
79 counter = buflen / 16; /* 16 用于计算 */ in hmac_wpi_encrypt()
87 for (loop = 0; loop < counter; loop++) { in hmac_wpi_encrypt()
/device/soc/hisilicon/hi3861v100/sdk_liteos/third_party/libcoap/include/coap2/
H A Dutlist.h406 #define LL_COUNT(head,el,counter) \
407 LL_COUNT2(head,el,counter,next) \
409 #define LL_COUNT2(head,el,counter,next) \
411 (counter) = 0; \
412 LL_FOREACH2(head,el,next) { ++(counter); } \
727 #define DL_COUNT(head,el,counter) \
728 DL_COUNT2(head,el,counter,next) \
730 #define DL_COUNT2(head,el,counter,next) \
732 (counter) = 0; \
733 DL_FOREACH2(head,el,next) { ++(counter); } \
[all...]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/tl/
H A Dmali_kbase_tlstream.c71 * @counter: value of packet counter for this packet's stream
76 static void kbasep_packet_number_update(char *buffer, u32 counter) in kbasep_packet_number_update() argument
80 memcpy(&buffer[PACKET_HEADER_SIZE], &counter, sizeof(counter)); in kbasep_packet_number_update()

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