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/device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/common/
H A Dmali_l2_cache.c19 * Size of the Mali L2 cache registers in bytes
24 * Mali L2 cache register numbers
43 * Mali L2 cache commands
44 * These are the commands that can be sent to the Mali L2 cache unit
51 * Mali L2 cache commands
52 * These are the commands that can be sent to the Mali L2 cache unit
61 * Mali L2 cache status bits
79 static void mali_l2_cache_reset(struct mali_l2_cache_core *cache);
82 struct mali_l2_cache_core *cache, u32 reg, u32 val);
84 static void mali_l2_cache_lock(struct mali_l2_cache_core *cache) in mali_l2_cache_lock() argument
90 mali_l2_cache_unlock(struct mali_l2_cache_core *cache) mali_l2_cache_unlock() argument
101 struct mali_l2_cache_core *cache = NULL; mali_l2_cache_create() local
166 mali_l2_cache_delete(struct mali_l2_cache_core *cache) mali_l2_cache_delete() argument
198 mali_l2_cache_power_up(struct mali_l2_cache_core *cache) mali_l2_cache_power_up() argument
213 mali_l2_cache_power_down(struct mali_l2_cache_core *cache) mali_l2_cache_power_down() argument
254 mali_l2_cache_core_set_counter_src( struct mali_l2_cache_core *cache, u32 source_id, u32 counter) mali_l2_cache_core_set_counter_src() argument
300 mali_l2_cache_core_get_counter_values( struct mali_l2_cache_core *cache, u32 *src0, u32 *value0, u32 *src1, u32 *value1) mali_l2_cache_core_get_counter_values() argument
356 mali_l2_cache_invalidate(struct mali_l2_cache_core *cache) mali_l2_cache_invalidate() argument
373 mali_l2_cache_invalidate_conditional( struct mali_l2_cache_core *cache, u32 id) mali_l2_cache_invalidate_conditional() argument
409 struct mali_l2_cache_core *cache = mali_global_l2s[i]; mali_l2_cache_invalidate_all() local
439 struct mali_l2_cache_core *cache = mali_global_l2s[i]; mali_l2_cache_invalidate_all_pages() local
468 mali_l2_cache_reset(struct mali_l2_cache_core *cache) mali_l2_cache_reset() argument
504 mali_l2_cache_send_command( struct mali_l2_cache_core *cache, u32 reg, u32 val) mali_l2_cache_send_command() argument
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H A Dmali_l2_cache.h18 /* Maximum 1 GP and 4 PP for an L2 cache core (Mali-400 MP4) */
22 * Definition of the L2 cache core struct
23 * Used to track a L2 cache unit in the system.
30 /* Synchronize L2 cache access */
36 /* The power domain this L2 cache belongs to */
39 /* MALI_TRUE if power is on for this L2 cache */
72 void mali_l2_cache_delete(struct mali_l2_cache_core *cache);
74 MALI_STATIC_INLINE u32 mali_l2_cache_get_id(struct mali_l2_cache_core *cache) in mali_l2_cache_get_id() argument
76 MALI_DEBUG_ASSERT_POINTER(cache); in mali_l2_cache_get_id()
77 return cache in mali_l2_cache_get_id()
80 mali_l2_cache_get_pm_domain( struct mali_l2_cache_core *cache) mali_l2_cache_get_pm_domain() argument
93 mali_l2_cache_core_get_counter_src0( struct mali_l2_cache_core *cache) mali_l2_cache_core_get_counter_src0() argument
100 mali_l2_cache_core_get_counter_src1( struct mali_l2_cache_core *cache) mali_l2_cache_core_get_counter_src1() argument
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H A Dmali_kernel_core.c73 /** Limits for the number of PP cores behind each L2 cache. */
222 MALI_DEBUG_PRINT(3, ("Found L2 cache %s\n", resource->description)); in mali_create_l2_cache_core()
226 MALI_PRINT_ERROR(("Failed to create L2 cache object\n")); in mali_create_l2_cache_core()
230 MALI_DEBUG_PRINT(3, ("Created L2 cache core object\n")); in mali_create_l2_cache_core()
242 MALI_DEBUG_PRINT(3, ("Did not find required Mali L2 cache in config file\n")); in mali_parse_config_l2_cache()
263 MALI_DEBUG_PRINT(3, ("Creating Mali-450 L2 cache core for GP\n")); in mali_parse_config_l2_cache()
269 MALI_DEBUG_PRINT(3, ("Did not find required Mali L2 cache for GP in config file\n")); in mali_parse_config_l2_cache()
275 MALI_DEBUG_PRINT(3, ("Creating Mali-450 L2 cache core for PP group 0\n")); in mali_parse_config_l2_cache()
281 MALI_DEBUG_PRINT(3, ("Did not find required Mali L2 cache for PP group 0 in config file\n")); in mali_parse_config_l2_cache()
287 MALI_DEBUG_PRINT(3, ("Creating Mali-450 L2 cache cor in mali_parse_config_l2_cache()
312 mali_create_group(struct mali_l2_cache_core *cache, _mali_osk_resource_t *resource_mmu, _mali_osk_resource_t *resource_gp, _mali_osk_resource_t *resource_pp, u32 domain_index) mali_create_group() argument
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/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/common/
H A Dmali_l2_cache.c20 * Size of the Mali L2 cache registers in bytes
25 * Mali L2 cache register numbers
44 * Mali L2 cache commands
45 * These are the commands that can be sent to the Mali L2 cache unit
52 * Mali L2 cache commands
53 * These are the commands that can be sent to the Mali L2 cache unit
62 * Mali L2 cache status bits
80 static void mali_l2_cache_reset(struct mali_l2_cache_core *cache);
82 static mali_osk_errcode_t mali_l2_cache_send_command(struct mali_l2_cache_core *cache, u32 reg, u32 val);
84 static void mali_l2_cache_lock(struct mali_l2_cache_core *cache) in mali_l2_cache_lock() argument
90 mali_l2_cache_unlock(struct mali_l2_cache_core *cache) mali_l2_cache_unlock() argument
100 struct mali_l2_cache_core *cache = NULL; mali_l2_cache_create() local
154 mali_l2_cache_delete(struct mali_l2_cache_core *cache) mali_l2_cache_delete() argument
186 mali_l2_cache_power_up(struct mali_l2_cache_core *cache) mali_l2_cache_power_up() argument
202 mali_l2_cache_power_down(struct mali_l2_cache_core *cache) mali_l2_cache_power_down() argument
238 mali_l2_cache_core_set_counter_src(struct mali_l2_cache_core *cache, u32 source_id, u32 counter) mali_l2_cache_core_set_counter_src() argument
281 mali_l2_cache_core_get_counter_values(struct mali_l2_cache_core *cache, u32 *src0, u32 *value0, u32 *src1, u32 *value1) mali_l2_cache_core_get_counter_values() argument
334 mali_l2_cache_invalidate(struct mali_l2_cache_core *cache) mali_l2_cache_invalidate() argument
350 mali_l2_cache_invalidate_conditional(struct mali_l2_cache_core *cache, u32 id) mali_l2_cache_invalidate_conditional() argument
382 struct mali_l2_cache_core *cache = mali_global_l2s[i]; mali_l2_cache_invalidate_all() local
409 struct mali_l2_cache_core *cache = mali_global_l2s[i]; mali_l2_cache_invalidate_all_pages() local
436 mali_l2_cache_reset(struct mali_l2_cache_core *cache) mali_l2_cache_reset() argument
462 mali_l2_cache_send_command(struct mali_l2_cache_core *cache, u32 reg, u32 val) mali_l2_cache_send_command() argument
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H A Dmali_l2_cache.h19 /* Maximum 1 GP and 4 PP for an L2 cache core (Mali-400 MP4) */
23 * Definition of the L2 cache core struct
24 * Used to track a L2 cache unit in the system.
31 /* Synchronize L2 cache access */
37 /* The power domain this L2 cache belongs to */
40 /* MALI_TRUE if power is on for this L2 cache */
72 void mali_l2_cache_delete(struct mali_l2_cache_core *cache);
74 MALI_STATIC_INLINE u32 mali_l2_cache_get_id(struct mali_l2_cache_core *cache) in mali_l2_cache_get_id() argument
76 MALI_DEBUG_ASSERT_POINTER(cache); in mali_l2_cache_get_id()
77 return cache in mali_l2_cache_get_id()
80 mali_l2_cache_get_pm_domain(struct mali_l2_cache_core *cache) mali_l2_cache_get_pm_domain() argument
91 mali_l2_cache_core_get_counter_src0(struct mali_l2_cache_core *cache) mali_l2_cache_core_get_counter_src0() argument
97 mali_l2_cache_core_get_counter_src1(struct mali_l2_cache_core *cache) mali_l2_cache_core_get_counter_src1() argument
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H A Dmali_kernel_core.c74 /** Limits for the number of PP cores behind each L2 cache. */
235 MALI_DEBUG_PRINT(MALI_KERNEL_LEVEL_MESSAGE, ("Found L2 cache %s\n", resource->description)); in mali_create_l2_cache_core()
239 MALI_PRINT_ERROR(("Failed to create L2 cache object\n")); in mali_create_l2_cache_core()
243 MALI_DEBUG_PRINT(MALI_KERNEL_LEVEL_MESSAGE, ("Created L2 cache core object\n")); in mali_create_l2_cache_core()
255 MALI_DEBUG_PRINT(MALI_KERNEL_LEVEL_MESSAGE, ("Did not find required Mali L2 cache in config file\n")); in mali_parse_config_l2_cache()
276 MALI_DEBUG_PRINT(MALI_KERNEL_LEVEL_MESSAGE, ("Creating Mali-450 L2 cache core for GP\n")); in mali_parse_config_l2_cache()
283 ("Did not find required Mali L2 cache for GP in config file\n")); in mali_parse_config_l2_cache()
289 MALI_DEBUG_PRINT(MALI_KERNEL_LEVEL_MESSAGE, ("Creating Mali-450 L2 cache core for PP group 0\n")); in mali_parse_config_l2_cache()
296 ("Did not find required Mali L2 cache for PP group 0 in config file\n")); in mali_parse_config_l2_cache()
302 MALI_DEBUG_PRINT(MALI_KERNEL_LEVEL_MESSAGE, ("Creating Mali-450 L2 cache cor in mali_parse_config_l2_cache()
327 mali_create_group(struct mali_l2_cache_core *cache, _mali_osk_resource_t *resource_mmu, _mali_osk_resource_t *resource_gp, _mali_osk_resource_t *resource_pp, u32 domain_index) mali_create_group() argument
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/device/soc/hisilicon/hi3861v100/sdk_liteos/third_party/mbedtls/include/mbedtls/
H A Dssl_cache.h4 * \brief SSL session cache implementation
52 #define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /*!< Maximum entries in cache */
65 * \brief This structure is used for storing cache entries
85 int timeout; /*!< cache entry timeout */
93 * \brief Initialize an SSL cache context
95 * \param cache SSL cache context
97 void mbedtls_ssl_cache_init( mbedtls_ssl_cache_context *cache );
103 * \param data SSL cache context
112 * \param data SSL cache contex
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/device/qemu/riscv32_virt/liteos_m/board/driver/video/
H A Dkey_cache.c103 static void KeyCacheInsert(struct KeyCache *cache, const char* name, int len) in KeyCacheInsert() argument
106 LOS_ListAdd(&g_keyCacheHashEntrys[hash], &cache->hashEntry); in KeyCacheInsert()
H A Dkey_cache.h87 struct fb_mem *fbmem; /* vnode points to the cache */
91 int hit; /* cache hit count */
97 int KeyCacheFree(struct KeyCache *cache);
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/osal/linux/mmz/
H A Dallocator.h45 void *(*mmf_map)(phys_addr_t phys, int len, int cache);
H A Dcma_allocator.c478 static void *__mmf_map(phys_addr_t phys, int len, int cache) argument
490 if (cache) {
496 if (cache) {
H A Dhisi_allocator.c479 static void *__mmf_map(phys_addr_t phys, int len, int cache) in __mmf_map() argument
482 if (cache) { in __mmf_map()
/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/boot/
H A Dstart.S74 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
97 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
99 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/boot/
H A Dstart.S74 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
97 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
99 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
/device/soc/hisilicon/hi3861v100/sdk_liteos/build/make_scripts/
H A Dconfig.mk34 CACHE_PATH := build/build_tmp/cache
/device/soc/hisilicon/hi3861v100/sdk_liteos/build/win_scripts/build/make_scripts/
H A Dconfig.mk34 CACHE_PATH := build/build_tmp/cache
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/
H A Dwl_cfgnan.c4740 WL_ERR(("%s: fail to cache svc info, ret=%d\n", in wl_cfgnan_svc_handler()
4827 /* terminate ranging sessions for this svc, avoid clearing svc cache */ in wl_cfgnan_subscribe_handler()
4835 /* Clear cache info in Firmware */ in wl_cfgnan_subscribe_handler()
4838 WL_ERR(("couldn't send clear cache to FW \n")); in wl_cfgnan_subscribe_handler()
4841 /* Invalidate local cache info */ in wl_cfgnan_subscribe_handler()
5016 /* clear svc cache for the service */ in wl_cfgnan_cancel_sub_handler()
6014 /* check in cache */ in wl_cfgnan_data_path_request_handler()
6015 nan_disc_result_cache *cache; in wl_cfgnan_data_path_request_handler() local
6016 cache = wl_cfgnan_get_disc_result(cfg, in wl_cfgnan_data_path_request_handler()
6018 if (!cache) { in wl_cfgnan_data_path_request_handler()
6466 wl_nan_cache_to_event_data(nan_disc_result_cache *cache, nan_event_data_t *nan_event_data, osl_t *osh) wl_nan_cache_to_event_data() argument
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H A Dwl_cfgvendor.c428 gscan_results_cache_t *cache = (gscan_results_cache_t *)data; in wl_cfgvendor_send_hotlist_event() local
456 while (cache && iter_cnt_to_send) { in wl_cfgvendor_send_hotlist_event()
457 ptr = (const void *) &cache->results[cache->tot_consumed]; in wl_cfgvendor_send_hotlist_event()
459 if (iter_cnt_to_send < (cache->tot_count - cache->tot_consumed)) { in wl_cfgvendor_send_hotlist_event()
462 cnt = (cache->tot_count - cache->tot_consumed); in wl_cfgvendor_send_hotlist_event()
466 cache->tot_consumed += cnt; in wl_cfgvendor_send_hotlist_event()
469 if (cache in wl_cfgvendor_send_hotlist_event()
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/device/soc/rockchip/rk3588/kernel/drivers/video/rockchip/rga3/include/
H A Drga_drv.h16 #include <linux/dma-buf-cache.h>
228 * In order to use the virtual address to refresh the cache,
/device/soc/rockchip/common/sdk_linux/
H A DMakefile913 KBUILD_LDFLAGS += --thinlto-cache-dir=$(extmod-prefix).thinlto-cache
1529 compile_commands.json .thinlto-cache
1789 $(KBUILD_EXTMOD)/compile_commands.json $(KBUILD_EXTMOD)/.thinlto-cache
/device/soc/rockchip/common/vendor/drivers/video/rockchip/mpp/
H A Dmpp_iommu.c12 #include <linux/dma-buf-cache.h>
/device/soc/rockchip/common/sdk_linux/arch/arm64/kernel/
H A Dcpuinfo.c8 #include <asm/cache.h>
344 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); in cpuinfo_detect_icache_policy()
/device/soc/rockchip/common/sdk_linux/drivers/irqchip/
H A Dirq-gic-v3-its.c2290 static int its_setup_baser(struct its_node *its, struct its_baser *baser, u64 cache, u64 shr, u32 order, bool indirect) in its_setup_baser() argument
2334 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | cache | shr | GITS_BASER_VALID); in its_setup_baser()
2371 cache = GITS_BASER_nC; in its_setup_baser()
2578 u64 cache = GITS_BASER_RaWaWb; in its_alloc_tables() local
2583 cache = GITS_BASER_nCnB; in its_alloc_tables()
2625 err = its_setup_baser(its, baser, cache, shr, order, indirect); in its_alloc_tables()
2632 cache = baser->val & GITS_BASER_CACHEABILITY_MASK; in its_alloc_tables()
3124 pr_info_once("GIC: using cache flushing for LPI property table\n"); in its_cpu_init_lpis()
4845 /* Restore GITS_BASER from the value cache. */ in its_restore_enable()
5098 pr_info("ITS: using cache flushin in its_probe_one()
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/device/soc/rockchip/common/sdk_linux/drivers/iommu/
H A Diommu.c2025 if (info->cache & ~mask) { in iommu_check_cache_invl_data()
2035 if (info->cache & IOMMU_CACHE_INV_TYPE_PASID) { in iommu_check_cache_invl_data()
2053 if (info->cache & IOMMU_CACHE_INV_TYPE_DEV_IOTLB) { in iommu_check_cache_invl_data()
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
H A Drockchip_drm_gem.c7 #include <linux/dma-buf-cache.h>

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