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Searched refs:bit_idx (Results 1 - 7 of 7) sorted by relevance

/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/oal/
H A Doal_util.c117 hi_u8 bit_idx; in oal_get_lut_index() local
128 for (bit_idx = 0; bit_idx < 8; bit_idx++) { /* 8 bit循环处理 */ in oal_get_lut_index()
129 if ((temp & (1 << bit_idx)) != 0) { in oal_get_lut_index()
133 index = (byte * 8 + bit_idx); /* 乘8转成bit index */ in oal_get_lut_index()
136 lut_index_table[byte] |= (hi_u8)(1 << bit_idx); in oal_get_lut_index()
/device/soc/rockchip/common/sdk_linux/include/linux/
H A Dclk-provider.h430 * @bit_idx: single bit controlling gate
437 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
451 u8 bit_idx; member
466 u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock);
468 void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock);
476 * @bit_idx: which bit in the register controls gating of this clock
480 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, clk_gate_flags, lock) \
481 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, NULL, (flags), (reg), (bit_idx), \
491 * @bit_idx: which bit in the register controls gating of this clock
495 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, bit_idx, clk_gate_flag
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/device/soc/rockchip/common/vendor/drivers/clk/
H A Dclk-dclk-divider.c127 gate->bit_idx = gate_shift; in rockchip_clk_register_dclk_branch()
/device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/
H A Dclk-dclk-divider.c134 gate->bit_idx = gate_shift; in rockchip_clk_register_dclk_branch()
H A Dclk-link.c65 gate->bit_idx = priv->shift; in register_clocks()
/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-half-divider.c182 gate->bit_idx = gate_shift; in rockchip_clk_register_halfdiv()
H A Dclk.c75 gate->bit_idx = gate_shift; in rockchip_clk_register_branch()
252 gate->bit_idx = gate_shift; in rockchip_clk_register_frac_branch()
348 gate->bit_idx = gate_shift; in rockchip_clk_register_factor_branch()

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