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Help
Searched
refs:W_CTL_BASE_ADDR
(Results
1 - 3
of
3
) sorted by relevance
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/commonboot/
H
A
D
hi3861_platform.h
132
#define
W_CTL_BASE_ADDR
0x40028000
macro
133
#define W_CTL_MAC_WDT_RST_SEL_REG (
W_CTL_BASE_ADDR
+ 0x0034)
134
#define W_CTL_PHY_WDT_RST_SEL_REG (
W_CTL_BASE_ADDR
+ 0x0038)
135
#define W_CTL_WDT_RST_SEL_REG (
W_CTL_BASE_ADDR
+ 0x003C)
136
#define W_CTL_CPU_MAC_CLK_DIV_REG (
W_CTL_BASE_ADDR
+ 0x0070)
137
#define W_CTL_UART01_CKDIV_OFFSET (
W_CTL_BASE_ADDR
+ 0x0074)
138
#define W_CTL_UART2_CKDIV_OFFSET (
W_CTL_BASE_ADDR
+ 0x0090)
139
#define W_CTL_W_TCXO_SEL_REG (
W_CTL_BASE_ADDR
+ 0x0118)
140
#define W_CTL_CLKMUX_STS_DIV_STS_REG (
W_CTL_BASE_ADDR
+ 0x0130)
/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H
A
D
hi3861_platform_base.h
73
#define
W_CTL_BASE_ADDR
0x40028000
macro
74
#define W_CTL_MAC_WDT_RST_SEL_REG (
W_CTL_BASE_ADDR
+ 0x34)
75
#define W_CTL_PHY_WDT_RST_SEL_REG (
W_CTL_BASE_ADDR
+ 0x38)
76
#define W_CTL_WDT_RST_SEL_REG (
W_CTL_BASE_ADDR
+ 0x3C)
77
#define W_CTL_UART_MAC80M_CLKEN_REG (
W_CTL_BASE_ADDR
+ 0x40)
78
#define W_CTL_WLPHY_CLKEN_CLKEN_REG (
W_CTL_BASE_ADDR
+ 0x4C)
79
#define W_CTL_CPU_MAC_CLK_DIV_REG (
W_CTL_BASE_ADDR
+ 0x70)
80
#define W_CTL_UART01_CKDIV_OFFSET (
W_CTL_BASE_ADDR
+ 0x74)
81
#define W_CTL_WLPHY_CLK_DIV_0_REG (
W_CTL_BASE_ADDR
+ 0x78)
82
#define W_CTL_WLPHY_CLK_DIV_1_REG (
W_CTL_BASE_ADDR
[all...]
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/tsensor/
H
A
D
hi_tsensor_pm.c
19
#define TSENSOR_BASE_ADDRESS (
W_CTL_BASE_ADDR
)
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