Searched refs:UART_IMSC (Results 1 - 13 of 13) sorted by relevance
| /device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/uart/ |
| H A D | uart_drv.c | 220 hi_u32 tx_status = hi_reg_read_val32(udd->phys_base + UART_IMSC); in uart_tx_interrupt_disable()
221 hi_reg_write32(udd->phys_base + UART_IMSC, (~UART_TX_INT_BIT) & tx_status); in uart_tx_interrupt_disable()
226 hi_u32 tx_status = hi_reg_read_val32(udd->phys_base + UART_IMSC); in uart_tx_interrupt_enable()
227 hi_reg_write32(udd->phys_base + UART_IMSC, (unsigned short) (UART_TX_INT_BIT | tx_status)); in uart_tx_interrupt_enable()
238 hi_u32 tx_status = hi_reg_read_val32(udd->phys_base + UART_IMSC); in uart_rx_interrupt_disable()
239 hi_reg_write32(udd->phys_base + UART_IMSC, ~(UART_RX_INT_ENABLE) & tx_status); in uart_rx_interrupt_disable()
244 hi_u32 tx_status = hi_reg_read_val32(udd->phys_base + UART_IMSC); in uart_rx_interrupt_enable()
245 hi_reg_write32(udd->phys_base + UART_IMSC, UART_RX_INT_ENABLE | tx_status); in uart_rx_interrupt_enable()
579 hi_reg_write32(udd->phys_base + UART_IMSC, 0); in uart_drv_startup()
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| H A D | hi_uart.c | 42 #define UART_IMSC 0x38 macro
497 temp = hi_reg_read_val16(phys_base + UART_IMSC); in hi_uart_lp_restore()
498 hi_reg_write16(phys_base + UART_IMSC, UART_RX_INT_ENABLE | temp); in hi_uart_lp_restore()
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| H A D | serial_dw.h | 82 #define UART_IMSC 0x38 macro
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| /device/qemu/arm_virt/liteos_a_mini/board/amba_pl011/ |
| H A D | amba_pl011.h | 52 #define UART_IMSC 0x38 /* interrupt mask register */
macro
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| H A D | amba_pl011.c | 196 UARTREG(UART_REG_BASE, UART_IMSC) = (1 << 4 | 1 << 6);
in uart_init()
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| /device/qemu/arm_virt/liteos_a/board/amba_pl011/ |
| H A D | amba_pl011.h | 52 #define UART_IMSC 0x38 /* interrupt mask register */
macro
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| H A D | amba_pl011.c | 196 UARTREG(UART_REG_BASE, UART_IMSC) = (1 << 4 | 1 << 6);
in uart_init()
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/fixed/include/ |
| H A D | serial_dw.h | 31 #define UART_IMSC 0x38 macro
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| /device/soc/hisilicon/common/platform/uart/ |
| H A D | uart_pl011.c | 242 OSAL_WRITEW(0x0, port->physBase + UART_IMSC); in Pl011StartUp()
251 OSAL_WRITEW(UART_IMSC_RX | UART_IMSC_TIMEOUT, port->physBase + UART_IMSC); in Pl011StartUp()
276 OSAL_WRITEW(0, port->physBase + UART_IMSC); in Pl011ShutDown()
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| H A D | uart_pl011.h | 45 #define UART_IMSC 0x38 /* interrupt mask register */ macro
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| H A D | uart_hi35xx.c | 46 {"UART_IMSC", PLATFORM_DUMPER_REGISTERL, (void *)(port->physBase + UART_IMSC)}, in UartDumperDump()
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| /device/qemu/drivers/uart/ |
| H A D | uart_pl011.c | 243 OSAL_WRITEW(0x0, port->physBase + UART_IMSC); in Pl011StartUp()
252 OSAL_WRITEW(UART_IMSC_RX | UART_IMSC_TIMEOUT, port->physBase + UART_IMSC); in Pl011StartUp()
277 OSAL_WRITEW(0, port->physBase + UART_IMSC); in Pl011ShutDown()
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| H A D | uart_pl011.h | 45 #define UART_IMSC 0x38 /* interrupt mask register */ macro
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