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Searched refs:UART0_REG_BASE (Results 1 - 17 of 17) sorted by relevance

/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/boot/
H A Duart.S33 .word UART0_REG_BASE
59 .word UART0_REG_BASE
95 .word UART0_REG_BASE
120 .word UART0_REG_BASE
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/boot/
H A Duart.S33 .word UART0_REG_BASE
59 .word UART0_REG_BASE
95 .word UART0_REG_BASE
120 .word UART0_REG_BASE
/device/qemu/arm_virt/liteos_a/board/include/asm/
H A Dplatform.h38 #define UART0_REG_BASE IO_DEVICE_ADDR(0x09000000) macro
41 #define UART_BASE UART0_REG_BASE
/device/qemu/arm_virt/liteos_a_mini/board/
H A Dtarget_config.h114 #define UART0_REG_BASE IO_DEVICE_ADDR(0x09000000) macro
116 #define UART_REG_BASE UART0_REG_BASE
/device/board/hisilicon/hispark_aries/liteos_a/board/
H A Dtarget_config.h112 #define UART0_REG_BASE IO_DEVICE_ADDR(0x12040000) macro
114 #define UART_REG_BASE UART0_REG_BASE
/device/qemu/arm_virt/liteos_a/board/
H A Dtarget_config.h114 #define UART0_REG_BASE IO_DEVICE_ADDR(0x09000000) macro
116 #define UART_REG_BASE UART0_REG_BASE
/device/board/hisilicon/hispark_taurus/liteos_a/board/
H A Dtarget_config.h120 #define UART0_REG_BASE IO_DEVICE_ADDR(UART0_REG_PBASE) macro
122 #define UART_REG_BASE UART0_REG_BASE
/device/soc/hisilicon/common/platform/dmac/
H A Ddmac_hi35xx.h44 #define UART0_RX_ADDR (UART0_REG_BASE + 0x0)
45 #define UART0_TX_ADDR (UART0_REG_BASE + 0x0)
/device/board/hisilicon/hispark_aries/liteos_a/board/include/asm/
H A Dplatform.h79 #define UART0_REG_BASE IO_DEVICE_ADDR(0x12040000) macro
88 #define UART_BASE UART0_REG_BASE
/device/board/hisilicon/hispark_aries/liteos_a/board/include/hisoc/
H A Ddmac.h158 { 4, UART0_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (4 << 1), PERI_8BIT_MODE},
161 { 5, UART0_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (5 << 1), PERI_8BIT_MODE},
H A Duart.h89 #define UART_REG_BASE UART0_REG_BASE
/device/board/hisilicon/hispark_taurus/liteos_a/board/include/hisoc/
H A Ddmac.h158 { 4, UART0_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (4 << 1), PERI_8BIT_MODE},
161 { 5, UART0_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (5 << 1), PERI_8BIT_MODE},
H A Duart.h92 #define UART_REG_BASE UART0_REG_BASE
/device/qemu/arm_virt/liteos_a/board/include/soc/
H A Duart.h43 #define UART_REG_BASE UART0_REG_BASE
/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/include/
H A Dplatform.h62 #define UART0_REG_BASE 0x12040000 macro
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/include/
H A Dplatform.h62 #define UART0_REG_BASE 0x120A0000 macro
/device/board/hisilicon/hispark_taurus/liteos_a/board/include/asm/
H A Dplatform.h92 #define UART0_REG_BASE IO_DEVICE_ADDR(UART0_REG_PBASE) macro

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