| /device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/ |
| H A D | rk3036-cru.h | 28 #define SCLK_TIMER0 85 macro
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| H A D | rk3128-cru.h | 31 #define SCLK_TIMER0 85 macro
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| H A D | rk3188-cru-common.h | 40 #define SCLK_TIMER0 84 macro
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| H A D | rk1808-cru.h | 88 #define SCLK_TIMER0 87 macro
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| H A D | px30-cru.h | 40 #define SCLK_TIMER0 38 macro
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| H A D | rk3288-cru.h | 40 #define SCLK_TIMER0 85 macro
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| /device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/ |
| H A D | rk1808-cru.h | 88 #define SCLK_TIMER0 87 macro
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 212 COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(2), 4, 1, MFLAGS,
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| H A D | clk-rk3128.c | 256 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
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| H A D | clk-rk3188.c | 369 GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS),
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| H A D | clk-rk3328.c | 352 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, RK3328_CLKGATE_CON(8), 5, GFLAGS),
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| H A D | clk-rv1108.c | 401 GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0, RV1108_CLKGATE_CON(1), 9, GFLAGS),
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| H A D | clk-rk3228.c | 292 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS),
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| H A D | clk-rk3308.c | 331 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, RK3308_CLKGATE_CON(3), 10, GFLAGS),
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| H A D | clk-rk3288.c | 296 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, RK3288_CLKGATE_CON(1), 0, GFLAGS),
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| H A D | clk-px30.c | 531 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, PX30_CLKGATE_CON(13), 0, GFLAGS),
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| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-rk1808.c | 694 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, RK1808_CLKGATE_CON(14), 8, GFLAGS),
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