PCLK_UART0_PMU (reference) in projects: device

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/device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/
H A D	px30-cru.h	`198 #define PCLK_UART0_PMU 21 macro 200 #define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1)`
H A D	rk1808-cru.h	`214 #define PCLK_UART0_PMU 293 macro`
/device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/
H A D	rk1808-cru.h	`214 #define PCLK_UART0_PMU 293 macro`
/device/soc/rockchip/common/vendor/drivers/clk/
H A D	clk-rk1808.c	`817 GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, RK1808_PMU_CLKGATE_CON(0), 7, GFLAGS),`
/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A D	clk-px30.c	`732 GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 7, GFLAGS),`