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Searched refs:GLB_CTL_TCXO_DIV_REG (Results 1 - 2 of 2) sorted by relevance

/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/commonboot/
H A Dhi3861_platform.h48 #define GLB_CTL_TCXO_DIV_REG (GLB_CTL_BASE + 0x74) macro
/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H A Dhi3861_platform_base.h153 #define GLB_CTL_TCXO_DIV_REG (GLB_CTL_BASE + 0x74) /* 24M/40M div reg */ macro

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