Searched refs:DIAG_CTL_BASE (Results 1 - 2 of 2) sorted by relevance

/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/commonboot/
H A D	hi3861_platform.h	143 #define DIAG_CTL_BASE 0x40060000 macro 144 #define DIAG_CTL_GP_REG0_REG (DIAG_CTL_BASE + 0x010) /* used to save rsa key */ 145 #define DIAG_CTL_GP_REG1_REG (DIAG_CTL_BASE + 0x014) /* used to save rsa key */ 146 #define DIAG_CTL_GP_REG2_REG (DIAG_CTL_BASE + 0x018) /* used to save ecc key */ 147 #define DIAG_CTL_GP_REG3_REG (DIAG_CTL_BASE + 0x01C) /* used to save ecc key */
/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H A D	hi3861_platform_base.h	425 #define DIAG_CTL_BASE 0x40060000 macro 426 #define DIAG_CTL_GP_REG0_REG (DIAG_CTL_BASE + 0x010) /* used to save rsa key */ 427 #define DIAG_CTL_GP_REG1_REG (DIAG_CTL_BASE + 0x014) /* used to save rsa key */ 428 #define DIAG_CTL_GP_REG2_REG (DIAG_CTL_BASE + 0x018) /* used to save ecc key */ 429 #define DIAG_CTL_GP_REG3_REG (DIAG_CTL_BASE + 0x01C) /* used to save ecc key */ 430 #define DIAG_CTL_DIAG_MUX (DIAG_CTL_BASE + 0x0BC) /* diag mux */ 431 #define DIAG_CTL_CLOCK_TEST_SEL (DIAG_CTL_BASE + 0x0D0) /* clock test div */ 432 #define DIAG_CTL_CLOCK_TEST_DIV (DIAG_CTL_BASE + 0x0D4) /* clock test div */ 433 #define DIAG_CTL_CLOCK_TEST_EN (DIAG_CTL_BASE + 0x0D8) /* clock test en */

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Indexes created Thu Nov 07 10:32:03 CST 2024