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Searched refs:CRG_REG_BASE (Results 1 - 25 of 33) sorted by relevance

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/device/board/hisilicon/hispark_aries/liteos_a/board/include/hisoc/
H A Dmmc.h58 #define PERI_CRG86 (CRG_REG_BASE + 0x158)
59 #define PERI_CRG87 (CRG_REG_BASE + 0x15C)
60 #define PERI_CRG94 (CRG_REG_BASE + 0x178)
61 #define PERI_CRG95 (CRG_REG_BASE + 0x17C)
62 #define PERI_CRG96 (CRG_REG_BASE + 0x180)
64 #define PERI_CRG106 (CRG_REG_BASE + 0x1A8)
65 #define PERI_CRG117 (CRG_REG_BASE + 0x01D4)
66 #define PERI_CRG123 (CRG_REG_BASE + 0x1EC)
67 #define PERI_CRG133 (CRG_REG_BASE + 0x214)
68 #define PERI_CRG143 (CRG_REG_BASE
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H A Dflash.h162 old_val = regval = readl(CRG_REG_BASE + REG_FMC_CRG); in hifmc100_set_system_clock()
179 writel(regval, (CRG_REG_BASE + REG_FMC_CRG)); in hifmc100_set_system_clock()
218 old_val = regval = readl(CRG_REG_BASE + REG_FMC_CRG); in hifmc100_nand_clk_enable()
229 writel(regval, (CRG_REG_BASE + REG_FMC_CRG)); in hifmc100_nand_clk_enable()
H A Duart.h60 tmp = GET_UINT32(CRG_REG_BASE + 0x0198); \
65 WRITE_UINT32(tmp, CRG_REG_BASE + 0x0198); \
H A Dclock.h27 #define PERI_CRG12 (CRG_REG_BASE + 0x30)
H A Dnet.h27 #define HIETH_CRG_IOBASE (CRG_REG_BASE + 0x016c)
H A Dnand.h27 #define PERI_CRG52 (CRG_REG_BASE + 0x00D0)
H A Dspinor.h28 #define PERI_CRG48 (CRG_REG_BASE + 0x00C0)
H A Dspinand.h49 unsigned base = CRG_REG_BASE; in hisnfc100_set_system_clock()
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/
H A Dddr_training_custom.c22 #define CRG_REG_BASE 0x12010000U macro
40 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
42 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
44 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
46 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
58 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
60 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
62 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
64 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
/device/board/hisilicon/hispark_taurus/liteos_a/board/include/hisoc/
H A Dmmc.h84 #define PERI_CRG49 (CRG_REG_BASE + 0xC4)
85 #define PERI_CRG50 (CRG_REG_BASE + 0xC8)
87 #define PERI_CRG82 (CRG_REG_BASE + 0x0148)
88 #define PERI_CRG83 (CRG_REG_BASE + 0x014C)
89 #define PERI_CRG84 (CRG_REG_BASE + 0x0150)
90 #define PERI_CRG85 (CRG_REG_BASE + 0x0154)
92 #define PERI_CRG86 (CRG_REG_BASE + 0x0158)
93 #define PERI_CRG87 (CRG_REG_BASE + 0x015C)
94 #define PERI_CRG88 (CRG_REG_BASE + 0x0160)
95 #define PERI_CRG89 (CRG_REG_BASE
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H A Dflash.h162 old_val = regval = readl(CRG_REG_BASE + REG_FMC_CRG); in hifmc100_set_system_clock()
179 writel(regval, (CRG_REG_BASE + REG_FMC_CRG)); in hifmc100_set_system_clock()
218 old_val = regval = readl(CRG_REG_BASE + REG_FMC_CRG); in hifmc100_nand_clk_enable()
229 writel(regval, (CRG_REG_BASE + REG_FMC_CRG)); in hifmc100_nand_clk_enable()
H A Dclock.h27 #define PERI_CRG12 (CRG_REG_BASE + 0x30)
H A Duart.h63 tmp = GET_UINT32(CRG_REG_BASE + 0x01B8); \
68 WRITE_UINT32(tmp, CRG_REG_BASE + 0x01B8); \
H A Dnet.h27 #define HIETH_CRG_IOBASE (CRG_REG_BASE + 0x016c)
H A Dnand.h27 #define PERI_CRG52 (CRG_REG_BASE + 0x00D0)
/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/drv/
H A Dddr_training_custom.c22 #define CRG_REG_BASE 0x12010000U macro
48 reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
50 ddr_write(reg->custom.ddrt_clk_reg | (1U << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
53 ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(1U << 0)), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
74 ddr_write(reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
95 ddr_cksel = (ddr_read(CRG_REG_BASE + PERI_CRG_DDRCKSEL) >> 0x3) & 0x7; in ddr_get_cksel()
/device/soc/hisilicon/common/platform/mmc/himci_v200/
H A Dhimci.h48 #define PERI_CRG49 (CRG_REG_BASE + 0xC4)
49 #define PERI_CRG50 (CRG_REG_BASE + 0xC8)
50 #define PERI_CRG82 (CRG_REG_BASE + 0x0148)
51 #define PERI_CRG83 (CRG_REG_BASE + 0x014C)
52 #define PERI_CRG84 (CRG_REG_BASE + 0x0150)
53 #define PERI_CRG85 (CRG_REG_BASE + 0x0154)
54 #define PERI_CRG86 (CRG_REG_BASE + 0x0158)
55 #define PERI_CRG87 (CRG_REG_BASE + 0x015C)
56 #define PERI_CRG88 (CRG_REG_BASE + 0x0160)
57 #define PERI_CRG89 (CRG_REG_BASE
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/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/boot/hi3518ev300/
H A Dlowlevel_init_v300.c89 reg_val = reg_get(CRG_REG_BASE + REG_PERI_CRG104); in trng_init()
91 reg_set(CRG_REG_BASE + REG_PERI_CRG104, reg_val); in trng_init()
103 reg_val = reg_get(CRG_REG_BASE + REG_PERI_CRG104); in trng_deinit()
105 reg_set(CRG_REG_BASE + REG_PERI_CRG104, reg_val); in trng_deinit()
291 #define CRG_REG_BASE 0x12010000 macro
318 reg->custom.ddrt_clk_reg = readl(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
320 writel(reg->custom.ddrt_clk_reg | (0x1 << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
323 writel(readl(CRG_REG_BASE + PERI_CRG_DDRT) & (~(0x1 << 0)), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
347 writel(reg->custom.ddrt_clk_reg, CRG_REG_BASE in ddr_boot_restore()
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/device/soc/hisilicon/common/platform/mmc/sdhci/
H A Dsdhci.h112 #define PERI_CRG125 (CRG_REG_BASE + 0x01F4)
113 #define PERI_CRG126 (CRG_REG_BASE + 0x01F8)
114 #define PERI_CRG127 (CRG_REG_BASE + 0x01FC)
115 #define PERI_CRG135 (CRG_REG_BASE + 0x021C)
116 #define PERI_CRG136 (CRG_REG_BASE + 0x0220)
117 #define PERI_CRG139 (CRG_REG_BASE + 0x022C)
118 #define PERI_SD_DRV_DLL_CTRL (CRG_REG_BASE + 0x210)
119 #define PERI_SDIO_DRV_DLL_CTRL (CRG_REG_BASE + 0x228)
120 #define PERI_SD_SAMPL_DLL_STATUS (CRG_REG_BASE + 0x208)
121 #define PERI_SDIO_SAMPL_DLL_STATUS (CRG_REG_BASE
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/device/qemu/arm_virt/liteos_a/board/include/soc/
H A Duart.h49 tmp = GET_UINT32(CRG_REG_BASE + 0x01B8); \
54 WRITE_UINT32(tmp, CRG_REG_BASE + 0x01B8); \
/device/soc/hisilicon/common/platform/dmac/
H A Ddmac_hi35xx.c307 tmp = OSAL_READL(CRG_REG_BASE + HIDMAC_PERI_CRG101_OFFSET); in HiDmacClkEn()
309 OSAL_WRITEL(tmp, CRG_REG_BASE + HIDMAC_PERI_CRG101_OFFSET); in HiDmacClkEn()
318 tmp = OSAL_READL(CRG_REG_BASE + HIDMAC_PERI_CRG101_OFFSET); in HiDmacUnReset()
320 OSAL_WRITEL(tmp, CRG_REG_BASE + HIDMAC_PERI_CRG101_OFFSET); in HiDmacUnReset()
322 tmp = OSAL_READL(CRG_REG_BASE + HIDMAC_PERI_CRG101_OFFSET); in HiDmacUnReset()
324 OSAL_WRITEL(tmp, CRG_REG_BASE + HIDMAC_PERI_CRG101_OFFSET); in HiDmacUnReset()
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/boot/
H A Dlowlevel_init_v300.c89 reg_val = reg_get(CRG_REG_BASE + REG_PERI_CRG104); in trng_init()
91 reg_set(CRG_REG_BASE + REG_PERI_CRG104, reg_val); in trng_init()
103 reg_val = reg_get(CRG_REG_BASE + REG_PERI_CRG104); in trng_deinit()
105 reg_set(CRG_REG_BASE + REG_PERI_CRG104, reg_val); in trng_deinit()
/device/qemu/arm_virt/liteos_a/board/include/asm/
H A Dplatform.h36 #define CRG_REG_BASE IO_DEVICE_ADDR(0x12010000) macro
/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/include/
H A Dplatform.h38 #define CRG_REG_BASE 0x12010000 macro
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/include/
H A Dplatform.h38 #define CRG_REG_BASE 0x12010000 macro

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