CLK_UART0_DIV (reference) in projects: device

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/device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/
H A D	rk3568-cru.h	`22 #define CLK_UART0_DIV 9 macro`
/device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/
H A D	rk3568-cru.h	`22 #define CLK_UART0_DIV 9 macro`
/device/soc/rockchip/rk3566/vendor/drivers/clk/
H A D	clk-rk3568.c	`1066 COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", ppll_usb480m_cpll_gpll_p, 0, RK3568_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0,`
/device/soc/rockchip/rk2206/hardware/lib/CMSIS/Device/RK2206/Include/
H A D	rk2206.h	`10881 #define CLK_UART0_DIV 0x05000004U macro 11217 CLK_UART0_PLL = CLK(CLK_UART0_PLL_SEL, CLK_UART0_DIV),`