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Searched refs:reg_idx (Results 1 - 25 of 25) sorted by relevance

/device/soc/rockchip/common/hardware/mpp/include/
H A Dmpp_device.h56 unsigned int reg_idx; member
62 unsigned int reg_idx; member
/device/soc/rockchip/rk3399/hardware/mpp/include/
H A Dmpp_device.h56 RK_U32 reg_idx; member
62 RK_U32 reg_idx; member
/device/soc/rockchip/rk3568/hardware/mpp/include/
H A Dmpp_device.h56 RK_U32 reg_idx; member
62 RK_U32 reg_idx; member
/third_party/mesa3d/src/gallium/drivers/svga/
H A Dsvga_pipe_streamout.c187 unsigned reg_idx = info->output[i].register_index; in svga_create_stream_output() local
190 shader->tgsi_info.output_semantic_name[reg_idx]; in svga_create_stream_output()
198 i, reg_idx, buf_idx, info->output[i].stream); in svga_create_stream_output()
257 shader->tgsi_info.output_semantic_index[reg_idx]; in svga_create_stream_output()
260 decls[numDecls].registerIndex = reg_idx; in svga_create_stream_output()
/third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/
H A Dir2.c105 insert(struct ir2_context *ctx, unsigned block_idx, unsigned reg_idx, in insert() argument
126 unsigned mr = ~(s->reg_state[reg_idx / 8] >> reg_idx % 8 * 4 & 0xf); in insert()
143 s->reg_state[reg_idx / 8] |= 1 << (*comp + reg_idx % 8 * 4); in insert()
H A Dir2_nir.c534 unsigned reg_idx = instr->reg - ctx->reg; /* XXX */ in load_input() local
536 instr->src[0] = ir2_src(reg_idx, 0, IR2_SRC_REG); in load_input()
720 unsigned reg_idx; in emit_tex() local
728 reg_idx = instr->reg - ctx->reg; /* hacky */ in emit_tex()
731 rcp->src[0] = ir2_src(reg_idx, IR2_SWIZZLE_Z, IR2_SRC_REG); in emit_tex()
735 coord_xy->src[0] = ir2_src(reg_idx, 0, IR2_SRC_REG); in emit_tex()
739 src_coord = ir2_src(reg_idx, 0, IR2_SRC_REG); in emit_tex()
/device/soc/rockchip/rk3588/hardware/mpp/include/
H A Dmpp_device.h61 RK_U32 reg_idx; member
74 RK_U32 reg_idx; member
/third_party/ffmpeg/libavcodec/
H A Dnvenc.c1928 int reg_idx = nvenc_register_frame(avctx, frame); in nvenc_upload_frame() local
1929 if (reg_idx < 0) { in nvenc_upload_frame()
1931 return reg_idx; in nvenc_upload_frame()
1938 if (!ctx->registered_frames[reg_idx].mapped) { in nvenc_upload_frame()
1939 ctx->registered_frames[reg_idx].in_map.version = NV_ENC_MAP_INPUT_RESOURCE_VER; in nvenc_upload_frame()
1940 ctx->registered_frames[reg_idx].in_map.registeredResource = ctx->registered_frames[reg_idx].regptr; in nvenc_upload_frame()
1941 nv_status = p_nvenc->nvEncMapInputResource(ctx->nvencoder, &ctx->registered_frames[reg_idx].in_map); in nvenc_upload_frame()
1948 ctx->registered_frames[reg_idx].mapped += 1; in nvenc_upload_frame()
1950 nvenc_frame->reg_idx in nvenc_upload_frame()
[all...]
H A Dnvenc.h84 int reg_idx; member
/third_party/mesa3d/src/gallium/drivers/lima/ir/gp/
H A Dregalloc.c366 int reg_idx; in assign_regs() local
367 BITSET_FOREACH_SET(reg_idx, block->live_out, ctx->comp->cur_reg) { in assign_regs()
368 if (BITSET_TEST(block->def_out, reg_idx)) { in assign_regs()
369 block->live_out_phys |= (1ull << ctx->registers[reg_idx].assigned_color); in assign_regs()
/device/soc/rockchip/common/vendor/drivers/video/rockchip/mpp/
H A Dmpp_rkvdec2.c165 u32 reg_idx, rcb_size, rcb_offset; in mpp_set_rcbbuf() local
175 reg_idx = rcb_inf->elem[i].index; in mpp_set_rcbbuf()
178 mpp_debug(DEBUG_SRAM_INFO, "rcb: reg %d use original buffer\n", reg_idx); in mpp_set_rcbbuf()
181 mpp_debug(DEBUG_SRAM_INFO, "rcb: reg %d offset %d, size %d\n", reg_idx, rcb_offset, rcb_size); in mpp_set_rcbbuf()
182 task->reg[reg_idx] = dec->rcb_iova + rcb_offset; in mpp_set_rcbbuf()
H A Dmpp_rkvenc2.c611 u32 reg_idx, rcb_size, rcb_offset; in rkvenc2_set_rcbbuf() local
616 reg_idx = rcb_inf->elem[i].index; in rkvenc2_set_rcbbuf()
623 mpp_debug(DEBUG_SRAM_INFO, "rcb: reg %d offset %d, size %d\n", reg_idx, rcb_offset, rcb_size); in rkvenc2_set_rcbbuf()
625 reg = rkvenc_get_class_reg(task, reg_idx * sizeof(u32)); in rkvenc2_set_rcbbuf()
H A Dmpp_common.h304 u32 reg_idx; member
H A Dmpp_common.c1457 mem_region->reg_idx = tbl[i]; in mpp_translate_reg_address()
1613 mpp_err("reg[%3d]: %pad, size %lx\n", mem->reg_idx, &mem->iova, mem->len); in mpp_task_dump_mem_region()
H A Dmpp_iep2.c260 mem_region->reg_idx = iep2_addr_rnum[i]; in iep2_process_reg_fd()
/device/soc/rockchip/rk3588/kernel/drivers/video/rockchip/mpp/
H A Dmpp_rkvdec2.c165 u32 reg_idx, rcb_size, rcb_offset; in mpp_set_rcbbuf() local
174 reg_idx = rcb_inf->elem[i].index; in mpp_set_rcbbuf()
178 "rcb: reg %d use original buffer\n", reg_idx); in mpp_set_rcbbuf()
182 reg_idx, rcb_offset, rcb_size); in mpp_set_rcbbuf()
183 task->reg[reg_idx] = dec->rcb_iova + rcb_offset; in mpp_set_rcbbuf()
H A Dmpp_rkvenc2.c603 u32 reg_idx, rcb_size, rcb_offset; in rkvenc2_set_rcbbuf() local
608 reg_idx = rcb_inf->elem[i].index; in rkvenc2_set_rcbbuf()
616 reg_idx, rcb_offset, rcb_size); in rkvenc2_set_rcbbuf()
618 reg = rkvenc_get_class_reg(task, reg_idx * sizeof(u32)); in rkvenc2_set_rcbbuf()
H A Dmpp_common.h276 u32 reg_idx; member
H A Dmpp_common.c1488 mem_region->reg_idx = tbl[i]; in mpp_translate_reg_address()
1661 mem->reg_idx, &mem->iova, mem->len); in mpp_task_dump_mem_region()
H A Dmpp_iep2.c274 mem_region->reg_idx = iep2_addr_rnum[i]; in iep2_process_reg_fd()
/third_party/pcre2/pcre2/src/sljit/
H A DsljitNativeX86_32.c1209 sljit_s32 i, next, reg_idx, offset; in sljit_emit_mem() local
1243 reg_idx = next > 0 ? i : (i ^ 0x1); in sljit_emit_mem()
1244 reg = regs[reg_idx]; in sljit_emit_mem()
1256 if ((mem & OFFS_REG_MASK) && (reg_idx == 1)) { in sljit_emit_mem()
H A DsljitNativeX86_64.c946 sljit_s32 i, next, reg_idx; in sljit_emit_mem() local
994 reg_idx = next > 0 ? i : (i ^ 0x1); in sljit_emit_mem()
995 reg = regs[reg_idx]; in sljit_emit_mem()
997 if ((mem & OFFS_REG_MASK) && (reg_idx == 1)) { in sljit_emit_mem()
/device/soc/rockchip/rk3568/hardware/mpp/mpp/legacy/
H A Dvpu.c43 RK_U32 reg_idx; member
/third_party/skia/third_party/externals/freetype/src/psaux/
H A Dcffdecode.c1917 FT_UInt reg_idx = (FT_UInt)args[0]; in FT_LOCAL_DEF() local
1927 if ( reg_idx <= 2 && in FT_LOCAL_DEF()
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_shader.c7507 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int offset, int eg_buffer_base) in r600_do_buffer_txq() argument
7511 int id = tgsi_tex_get_src_gpr(ctx, reg_idx) + offset; in r600_do_buffer_txq()
7512 int sampler_index_mode = inst->Src[reg_idx].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE in r600_do_buffer_txq()

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