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/kernel/linux/linux-5.10/drivers/soc/renesas/
H A Dr8a77980-sysc.c30 { "a2ir0", 0x400, 0, R8A77980_PD_A2IR0, R8A77980_PD_A3IR },
31 { "a2ir1", 0x400, 1, R8A77980_PD_A2IR1, R8A77980_PD_A3IR },
32 { "a2ir2", 0x400, 2, R8A77980_PD_A2IR2, R8A77980_PD_A3IR },
33 { "a2ir3", 0x400, 3, R8A77980_PD_A2IR3, R8A77980_PD_A3IR },
34 { "a2ir4", 0x400, 4, R8A77980_PD_A2IR4, R8A77980_PD_A3IR },
35 { "a2ir5", 0x400, 5, R8A77980_PD_A2IR5, R8A77980_PD_A3IR },
36 { "a2sc0", 0x400, 6, R8A77980_PD_A2SC0, R8A77980_PD_A3IR },
37 { "a2sc1", 0x400, 7, R8A77980_PD_A2SC1, R8A77980_PD_A3IR },
38 { "a2sc2", 0x400, 8, R8A77980_PD_A2SC2, R8A77980_PD_A3IR },
39 { "a2sc3", 0x400,
[all...]
H A Dr8a77970-sysc.c24 { "a2ir0", 0x400, 0, R8A77970_PD_A2IR0, R8A77970_PD_A3IR },
25 { "a2ir1", 0x400, 1, R8A77970_PD_A2IR1, R8A77970_PD_A3IR },
26 { "a2dp", 0x400, 2, R8A77970_PD_A2DP, R8A77970_PD_A3IR },
27 { "a2cn", 0x400, 3, R8A77970_PD_A2CN, R8A77970_PD_A3IR },
28 { "a2sc0", 0x400, 4, R8A77970_PD_A2SC0, R8A77970_PD_A3IR },
29 { "a2sc1", 0x400, 5, R8A77970_PD_A2SC1, R8A77970_PD_A3IR },
/kernel/linux/linux-6.6/drivers/pmdomain/renesas/
H A Dr8a77980-sysc.c31 { "a2ir0", 0x400, 0, R8A77980_PD_A2IR0, R8A77980_PD_A3IR },
32 { "a2ir1", 0x400, 1, R8A77980_PD_A2IR1, R8A77980_PD_A3IR },
33 { "a2ir2", 0x400, 2, R8A77980_PD_A2IR2, R8A77980_PD_A3IR },
34 { "a2ir3", 0x400, 3, R8A77980_PD_A2IR3, R8A77980_PD_A3IR },
35 { "a2ir4", 0x400, 4, R8A77980_PD_A2IR4, R8A77980_PD_A3IR },
36 { "a2ir5", 0x400, 5, R8A77980_PD_A2IR5, R8A77980_PD_A3IR },
37 { "a2sc0", 0x400, 6, R8A77980_PD_A2SC0, R8A77980_PD_A3IR },
38 { "a2sc1", 0x400, 7, R8A77980_PD_A2SC1, R8A77980_PD_A3IR },
39 { "a2sc2", 0x400, 8, R8A77980_PD_A2SC2, R8A77980_PD_A3IR },
40 { "a2sc3", 0x400,
[all...]
H A Dr8a77970-sysc.c24 { "a2ir0", 0x400, 0, R8A77970_PD_A2IR0, R8A77970_PD_A3IR },
25 { "a2ir1", 0x400, 1, R8A77970_PD_A2IR1, R8A77970_PD_A3IR },
26 { "a2dp", 0x400, 2, R8A77970_PD_A2DP, R8A77970_PD_A3IR },
27 { "a2cn", 0x400, 3, R8A77970_PD_A2CN, R8A77970_PD_A3IR },
28 { "a2sc0", 0x400, 4, R8A77970_PD_A2SC0, R8A77970_PD_A3IR },
29 { "a2sc1", 0x400, 5, R8A77970_PD_A2SC1, R8A77970_PD_A3IR },
/kernel/linux/linux-5.10/sound/soc/uniphier/
H A Daio-reg.h66 #define IPORTMXCTR1(n) (0x22000 + 0x400 * (n))
97 #define IPORTMXCTR2(n) (0x22004 + 0x400 * (n))
120 #define IPORTMXCNTCTR(n) (0x22010 + 0x400 * (n))
121 #define IPORTMXCOUNTER(n) (0x22014 + 0x400 * (n))
122 #define IPORTMXCNTMONI(n) (0x22018 + 0x400 * (n))
123 #define IPORTMXACLKSEL0EX(n) (0x22020 + 0x400 * (n))
127 #define IPORTMXEXNOE(n) (0x22070 + 0x400 * (n))
131 #define IPORTMXMASK(n) (0x22078 + 0x400 * (n))
138 #define IPORTMXRSTCTR(n) (0x2207c + 0x400 * (n))
187 #define OPORTMXCTR1(n) (0x42000 + 0x400 * (
[all...]
/kernel/linux/linux-6.6/sound/soc/uniphier/
H A Daio-reg.h66 #define IPORTMXCTR1(n) (0x22000 + 0x400 * (n))
97 #define IPORTMXCTR2(n) (0x22004 + 0x400 * (n))
120 #define IPORTMXCNTCTR(n) (0x22010 + 0x400 * (n))
121 #define IPORTMXCOUNTER(n) (0x22014 + 0x400 * (n))
122 #define IPORTMXCNTMONI(n) (0x22018 + 0x400 * (n))
123 #define IPORTMXACLKSEL0EX(n) (0x22020 + 0x400 * (n))
127 #define IPORTMXEXNOE(n) (0x22070 + 0x400 * (n))
131 #define IPORTMXMASK(n) (0x22078 + 0x400 * (n))
138 #define IPORTMXRSTCTR(n) (0x2207c + 0x400 * (n))
187 #define OPORTMXCTR1(n) (0x42000 + 0x400 * (
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/kmb/
H A Dkmb_regs.h110 #define LCD_LAYERn_CFG(N) (LCD_LAYER0_CFG + (0x400 * (N)))
177 #define LCD_LAYERn_COL_START(N) (LCD_LAYER0_COL_START + (0x400 * (N)))
179 #define LCD_LAYERn_ROW_START(N) (LCD_LAYER0_ROW_START + (0x400 * (N)))
181 #define LCD_LAYERn_WIDTH(N) (LCD_LAYER0_WIDTH + (0x400 * (N)))
183 #define LCD_LAYERn_HEIGHT(N) (LCD_LAYER0_HEIGHT + (0x400 * (N)))
185 #define LCD_LAYERn_SCALE_CFG(N) (LCD_LAYER0_SCALE_CFG + (0x400 * (N)))
187 #define LCD_LAYERn_ALPHA(N) (LCD_LAYER0_ALPHA + (0x400 * (N)))
190 (0x400 * (N)))
193 (0x400 * (N)))
196 (0x400 * (
[all...]
/kernel/linux/linux-6.6/drivers/misc/mchp_pci1xxxx/
H A Dmchp_pci1xxxx_gpio.c17 #define OUT_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400)
18 #define INP_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x10)
19 #define OUT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x20)
20 #define INP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x30)
21 #define PULLUP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x40)
22 #define PULLDOWN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x50)
23 #define OPENDRAIN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x60)
24 #define WAKEMASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x70)
25 #define MODE_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x80)
26 #define INTR_LO_TO_HI_EDGE_CONFIG(x) ((((x) / 32) * 4) + 0x400
[all...]
/kernel/linux/linux-5.10/arch/alpha/include/asm/
H A Ddma.h144 #define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG)
156 #define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG)
184 #define DMA_HIPAGE_0 (0x400 | DMA_PAGE_0)
185 #define DMA_HIPAGE_1 (0x400 | DMA_PAGE_1)
186 #define DMA_HIPAGE_2 (0x400 | DMA_PAGE_2)
187 #define DMA_HIPAGE_3 (0x400 | DMA_PAGE_3)
188 #define DMA_HIPAGE_4 (0x400 | DMA_PAGE_4)
189 #define DMA_HIPAGE_5 (0x400 | DMA_PAGE_5)
190 #define DMA_HIPAGE_6 (0x400 | DMA_PAGE_6)
191 #define DMA_HIPAGE_7 (0x400 | DMA_PAGE_
[all...]
/kernel/linux/linux-6.6/arch/alpha/include/asm/
H A Ddma.h144 #define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG)
156 #define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG)
184 #define DMA_HIPAGE_0 (0x400 | DMA_PAGE_0)
185 #define DMA_HIPAGE_1 (0x400 | DMA_PAGE_1)
186 #define DMA_HIPAGE_2 (0x400 | DMA_PAGE_2)
187 #define DMA_HIPAGE_3 (0x400 | DMA_PAGE_3)
188 #define DMA_HIPAGE_4 (0x400 | DMA_PAGE_4)
189 #define DMA_HIPAGE_5 (0x400 | DMA_PAGE_5)
190 #define DMA_HIPAGE_6 (0x400 | DMA_PAGE_6)
191 #define DMA_HIPAGE_7 (0x400 | DMA_PAGE_
[all...]
/kernel/linux/linux-5.10/drivers/misc/habanalabs/include/gaudi/asic_reg/
H A Dmme0_qm_masks.h84 #define MME0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400
86 #define MME0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400
88 #define MME0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400
90 #define MME0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400
92 #define MME0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400
106 #define MME0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400
108 #define MME0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400
110 #define MME0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400
112 #define MME0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400
114 #define MME0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400
[all...]
H A Ddma0_qm_masks.h84 #define DMA0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400
86 #define DMA0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400
88 #define DMA0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400
90 #define DMA0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400
92 #define DMA0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400
106 #define DMA0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400
108 #define DMA0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400
110 #define DMA0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400
112 #define DMA0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400
114 #define DMA0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400
[all...]
H A Dtpc0_qm_masks.h84 #define TPC0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400
86 #define TPC0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400
88 #define TPC0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400
90 #define TPC0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400
92 #define TPC0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400
106 #define TPC0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400
108 #define TPC0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400
110 #define TPC0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400
112 #define TPC0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400
114 #define TPC0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400
[all...]
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Ddma0_qm_masks.h84 #define DMA0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400
86 #define DMA0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400
88 #define DMA0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400
90 #define DMA0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400
92 #define DMA0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400
106 #define DMA0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400
108 #define DMA0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400
110 #define DMA0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400
112 #define DMA0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400
114 #define DMA0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400
[all...]
H A Dmme0_qm_masks.h84 #define MME0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400
86 #define MME0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400
88 #define MME0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400
90 #define MME0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400
92 #define MME0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400
106 #define MME0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400
108 #define MME0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400
110 #define MME0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400
112 #define MME0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400
114 #define MME0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400
[all...]
H A Dtpc0_qm_masks.h84 #define TPC0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400
86 #define TPC0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400
88 #define TPC0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400
90 #define TPC0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400
92 #define TPC0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400
106 #define TPC0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400
108 #define TPC0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400
110 #define TPC0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400
112 #define TPC0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400
114 #define TPC0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400
[all...]
H A Dnic0_qm0_masks.h84 #define NIC0_QM0_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400
86 #define NIC0_QM0_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400
88 #define NIC0_QM0_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400
90 #define NIC0_QM0_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400
92 #define NIC0_QM0_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400
106 #define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400
108 #define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400
110 #define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400
112 #define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400
114 #define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400
[all...]
/kernel/linux/linux-5.10/drivers/clk/hisilicon/
H A Dclk-hi6220.c156 { HI6220_HIFI_SRC, "hifi_src", hifi_src, ARRAY_SIZE(hifi_src), CLK_SET_RATE_PARENT, 0x400, 0, 1, CLK_MUX_HIWORD_MASK,},
157 { HI6220_UART1_SRC, "uart1_src", uart1_src, ARRAY_SIZE(uart1_src), CLK_SET_RATE_PARENT, 0x400, 1, 1, CLK_MUX_HIWORD_MASK,},
158 { HI6220_UART2_SRC, "uart2_src", uart2_src, ARRAY_SIZE(uart2_src), CLK_SET_RATE_PARENT, 0x400, 2, 1, CLK_MUX_HIWORD_MASK,},
159 { HI6220_UART3_SRC, "uart3_src", uart3_src, ARRAY_SIZE(uart3_src), CLK_SET_RATE_PARENT, 0x400, 3, 1, CLK_MUX_HIWORD_MASK,},
160 { HI6220_UART4_SRC, "uart4_src", uart4_src, ARRAY_SIZE(uart4_src), CLK_SET_RATE_PARENT, 0x400, 4, 1, CLK_MUX_HIWORD_MASK,},
161 { HI6220_MMC0_MUX0, "mmc0_mux0", mmc0_mux0_p, ARRAY_SIZE(mmc0_mux0_p), CLK_SET_RATE_PARENT, 0x400, 5, 1, CLK_MUX_HIWORD_MASK,},
162 { HI6220_MMC1_MUX0, "mmc1_mux0", mmc1_mux0_p, ARRAY_SIZE(mmc1_mux0_p), CLK_SET_RATE_PARENT, 0x400, 11, 1, CLK_MUX_HIWORD_MASK,},
163 { HI6220_MMC2_MUX0, "mmc2_mux0", mmc2_mux0_p, ARRAY_SIZE(mmc2_mux0_p), CLK_SET_RATE_PARENT, 0x400, 12, 1, CLK_MUX_HIWORD_MASK,},
164 { HI6220_MMC0_MUX1, "mmc0_mux1", mmc0_mux1_p, ARRAY_SIZE(mmc0_mux1_p), CLK_SET_RATE_PARENT, 0x400, 13, 1, CLK_MUX_HIWORD_MASK,},
165 { HI6220_MMC1_MUX1, "mmc1_mux1", mmc1_mux1_p, ARRAY_SIZE(mmc1_mux1_p), CLK_SET_RATE_PARENT, 0x400, 1
[all...]
/kernel/linux/linux-6.6/drivers/clk/hisilicon/
H A Dclk-hi6220.c153 { HI6220_HIFI_SRC, "hifi_src", hifi_src, ARRAY_SIZE(hifi_src), CLK_SET_RATE_PARENT, 0x400, 0, 1, CLK_MUX_HIWORD_MASK,},
154 { HI6220_UART1_SRC, "uart1_src", uart1_src, ARRAY_SIZE(uart1_src), CLK_SET_RATE_PARENT, 0x400, 1, 1, CLK_MUX_HIWORD_MASK,},
155 { HI6220_UART2_SRC, "uart2_src", uart2_src, ARRAY_SIZE(uart2_src), CLK_SET_RATE_PARENT, 0x400, 2, 1, CLK_MUX_HIWORD_MASK,},
156 { HI6220_UART3_SRC, "uart3_src", uart3_src, ARRAY_SIZE(uart3_src), CLK_SET_RATE_PARENT, 0x400, 3, 1, CLK_MUX_HIWORD_MASK,},
157 { HI6220_UART4_SRC, "uart4_src", uart4_src, ARRAY_SIZE(uart4_src), CLK_SET_RATE_PARENT, 0x400, 4, 1, CLK_MUX_HIWORD_MASK,},
158 { HI6220_MMC0_MUX0, "mmc0_mux0", mmc0_mux0_p, ARRAY_SIZE(mmc0_mux0_p), CLK_SET_RATE_PARENT, 0x400, 5, 1, CLK_MUX_HIWORD_MASK,},
159 { HI6220_MMC1_MUX0, "mmc1_mux0", mmc1_mux0_p, ARRAY_SIZE(mmc1_mux0_p), CLK_SET_RATE_PARENT, 0x400, 11, 1, CLK_MUX_HIWORD_MASK,},
160 { HI6220_MMC2_MUX0, "mmc2_mux0", mmc2_mux0_p, ARRAY_SIZE(mmc2_mux0_p), CLK_SET_RATE_PARENT, 0x400, 12, 1, CLK_MUX_HIWORD_MASK,},
161 { HI6220_MMC0_MUX1, "mmc0_mux1", mmc0_mux1_p, ARRAY_SIZE(mmc0_mux1_p), CLK_SET_RATE_PARENT, 0x400, 13, 1, CLK_MUX_HIWORD_MASK,},
162 { HI6220_MMC1_MUX1, "mmc1_mux1", mmc1_mux1_p, ARRAY_SIZE(mmc1_mux1_p), CLK_SET_RATE_PARENT, 0x400, 1
[all...]
/third_party/mesa3d/src/etnaviv/drm-shim/
H A Detnaviv_noop.c46 [ETNAVIV_PARAM_GPU_MODEL] = 0x400,
85 [ETNAVIV_PARAM_GPU_THREAD_COUNT] = 0x400,
112 [ETNAVIV_PARAM_GPU_THREAD_COUNT] = 0x400,
116 [ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE] = 0x400,
139 [ETNAVIV_PARAM_GPU_THREAD_COUNT] = 0x400,
143 [ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE] = 0x400,
/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb/
H A Dmv88e1xxx.h11 # define ADVERTISE_PAUSE 0x400
24 #define GBCR_PREFER_MASTER 0x400
29 #define GBSR_LP_1000HALF 0x400
/kernel/linux/linux-6.6/drivers/net/ethernet/chelsio/cxgb/
H A Dmv88e1xxx.h11 # define ADVERTISE_PAUSE 0x400
24 #define GBCR_PREFER_MASTER 0x400
29 #define GBSR_LP_1000HALF 0x400
/kernel/linux/linux-5.10/arch/mips/netlogic/xlr/
H A Dplatform.c182 xls_usb_ehci_device.resource[0].end = memres + 0x400 - 1; in xls_platform_usb_init()
185 memres += 0x400; in xls_platform_usb_init()
187 xls_usb_ohci_device_0.resource[0].end = memres + 0x400 - 1; in xls_platform_usb_init()
190 memres += 0x400; in xls_platform_usb_init()
192 xls_usb_ohci_device_1.resource[0].end = memres + 0x400 - 1; in xls_platform_usb_init()
/kernel/linux/linux-5.10/drivers/misc/habanalabs/include/goya/asic_reg/
H A Ddma_qm_0_masks.h46 #define DMA_QM_0_GLBL_CFG1_CP_FLUSH_MASK 0x400
90 #define DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400
110 #define DMA_QM_0_GLBL_SECURE_PROPS_MMBP_MASK 0x400
116 #define DMA_QM_0_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400
154 #define DMA_QM_0_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400
H A Dmme_cmdq_masks.h46 #define MME_CMDQ_GLBL_CFG1_CP_FLUSH_MASK 0x400
90 #define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400
110 #define MME_CMDQ_GLBL_SECURE_PROPS_MMBP_MASK 0x400
116 #define MME_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400
154 #define MME_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400

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