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Searched refs:isReg (Results 1 - 25 of 327) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsInstPrinter.cpp31 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() function
32 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
128 if (Op.isReg()) { in printOperand()
226 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && in printAlias()
228 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS)); in printAlias()
231 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); in printAlias()
235 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
238 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
241 return isReg<Mip in printAlias()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DMachineOperand.h220 return isReg() ? 0 : SubReg_TargetFlags; in getTargetFlags()
223 assert(!isReg() && "Register operands can't have target flags"); in setTargetFlags()
228 assert(!isReg() && "Register operands can't have target flags"); in addTargetFlag()
318 /// isReg - Tests if this is a MO_Register operand.
319 bool isReg() const { return OpKind == MO_Register; } in isReg() function
359 assert(isReg() && "This is not a register operand!"); in getReg()
364 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg()
369 assert(isReg() && "Wrong MachineOperand accessor"); in isUse()
374 assert(isReg() && "Wrong MachineOperand accessor"); in isDef()
379 assert(isReg() in isImplicit()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp112 if (MCOp.isReg()) in getMachineOpValue()
146 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
150 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && in adjustPqBits()
154 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
193 assert(Op1.isReg() && "First operand is not register."); in getRiMemoryOpValue()
225 assert(Op1.isReg() && "First operand is not register."); in getRrMemoryOpValue()
227 assert(Op2.isReg() && "Second operand is not register."); in getRrMemoryOpValue()
264 assert(Op1.isReg() && "First operand is not register."); in getSplsOpValue()
292 if (MCOp.isReg() || MCO in getBranchTargetOpValue()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp47 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
59 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
72 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
85 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
97 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
110 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
128 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
146 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIX16Encoding()
168 assert(MI.getOperand(OpNo+1).isReg()); in getSPE8DisEncoding()
183 assert(MI.getOperand(OpNo+1).isReg()); in getSPE4DisEncoding()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMasking.cpp68 if (Src.isReg() && in isCopyFromExec()
84 if (Dst.isReg() && in isCopyToExec()
86 MI.getOperand(1).isReg()) in isCopyToExec()
111 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
114 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
127 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
130 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
394 if (Src0.isReg() && Src0.getReg() == CopyFromExec) { in runOnMachineFunction()
396 } else if (Src1.isReg() && Src1.getReg() == CopyFromExec) { in runOnMachineFunction()
H A DSIFoldOperands.cpp53 assert(FoldOp->isReg() || FoldOp->isGlobal()); in FoldCandidate()
66 bool isReg() const { in isReg() function
190 assert(Old.isReg()); in updateOperand()
390 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() || in tryAddToFoldList()
391 !MI->getOperand(CommuteIdx1).isReg())) in tryAddToFoldList()
409 if (!OtherOp.isReg() || in tryAddToFoldList()
480 assert (Sub->isReg()); in getRegSeqInit()
483 SubDef && Sub->isReg() && !Sub->getSubReg() && in getRegSeqInit()
492 if (!Op->isReg()) in getRegSeqInit()
524 if (!OpToFold.isReg()) in tryToFoldACImm()
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H A DSIOptimizeExecMaskingPreRA.cpp113 if (Op->isReg() && Op->getReg() != Exec) in getOrNonExecReg()
116 if (Op->isReg() && Op->getReg() != Exec) in getOrNonExecReg()
211 !And->getOperand(1).isReg() || !And->getOperand(2).isReg()) in optimizeVcndVcmpPair()
233 if (Op1->isImm() && Op2->isReg()) in optimizeVcndVcmpPair()
235 if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1) in optimizeVcndVcmpPair()
250 if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() || in optimizeVcndVcmpPair()
358 if (Op.isReg()) in runOnMachineFunction()
399 if (Op.isReg()) in runOnMachineFunction()
H A DSIPeepholeSDWA.cpp115 assert(Target->isReg()); in SDWAOperand()
116 assert(Replaced->isReg()); in SDWAOperand()
272 assert(To.isReg() && From.isReg()); in copyRegOperand()
284 return LHS.isReg() && in isSameReg()
285 RHS.isReg() && in isSameReg()
292 if (!Reg->isReg() || !Reg->isDef()) in findSingleRegUse()
314 if (!Reg->isReg()) in findSingleRegDef()
322 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg()) in findSingleRegDef()
373 assert(Src && (Src->isReg() || Sr in convertToSDWA()
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H A DSIShrinkInstructions.cpp79 if (Src0.isReg()) { in foldImmediates()
177 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) in copyExtraImplicitOps()
185 if (!MI.getOperand(0).isReg()) in shrinkScalarCompare()
280 if (MI.getOperand(i).isReg() && MI.getOperand(i).isTied() && in shrinkMIMG()
363 if (Register::isVirtualRegister(Dest->getReg()) && SrcReg->isReg()) { in shrinkScalarLogicOp()
369 if (SrcReg->isReg() && SrcReg->getReg() == Dest->getReg()) { in shrinkScalarLogicOp()
393 if (!MO.isReg()) in instAccessReg()
464 if (!Xop.isReg()) in matchSwap()
638 if (!Src0->isReg() && Src1->isReg()) { in runOnMachineFunction()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DMachineInstr.cpp163 if (MO.isReg()) in RemoveRegOperandsFromUseLists()
172 if (MO.isReg()) in AddRegOperandsToUseLists()
219 bool isImpReg = Op.isReg() && Op.isImplicit(); in addOperand()
221 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { in addOperand()
267 if (NewMO->isReg()) { in addOperand()
302 if (Operands[i].isReg()) in RemoveOperand()
307 if (MRI && Operands[OpNo].isReg()) in RemoveOperand()
617 if (!MO.isReg()) { in isIdenticalTo()
684 if (!MO.isReg() || !MO.isDef()) in eraseFromParentAndMarkDBGValuesForRemoval()
711 if (MO.isReg() in getNumExplicitOperands()
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H A DImplicitNullChecks.cpp279 if (!(MOA.isReg() && MOA.getReg())) in canReorder()
284 if (!(MOB.isReg() && MOB.getReg())) in canReorder()
370 !BaseOp->isReg() || BaseOp->getReg() != PointerReg) in isSuitableMemoryOp()
417 if (!(DependenceMO.isReg() && DependenceMO.getReg())) in canHoistInst()
478 if (!(MBP.LHS.isReg() && MBP.RHS.isImm() && MBP.RHS.getImm() == 0 && in analyzeBlockForNullChecks()
602 return MO.isReg() && MO.getReg() && MO.isDef() && in analyzeBlockForNullChecks()
644 if (MO.isReg()) { in insertFaultingInstr()
691 if (!MO.isReg() || !MO.isDef()) in rewriteNullChecks()
701 if (!MO.isReg() || !MO.getReg() || !MO.isDef() || MO.isDead()) in rewriteNullChecks()
H A DMIRCanonicalizerPass.cpp167 if (!MO.isReg()) in rescheduleCanonically()
187 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg())) in rescheduleCanonically()
199 if (II->getOperand(i).isReg()) { in rescheduleCanonically()
315 if (!MI->getOperand(0).isReg()) in propagateLocalCopies()
317 if (!MI->getOperand(1).isReg()) in propagateLocalCopies()
355 if (!MO.isReg()) in doDefKillClear()
H A DDeadMachineInstructionElim.cpp78 if (MO.isReg() && MO.isDef()) { in isDead()
152 if (MO.isReg() && MO.isDef()) { in runOnMachineFunction()
171 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
H A DMachineCopyPropagation.cpp455 if (&MIUse != &Use && MIUse.isReg() && MIUse.isImplicit() && in hasImplicitOverlap()
479 if (!MOUse.isReg() || MOUse.isTied() || MOUse.isUndef() || MOUse.isDef() || in forwardUses()
598 if (!MO.isReg() || !MO.readsReg()) in ForwardCopyPropagateBlock()
621 if (!MO.isReg() || !MO.isDef()) in ForwardCopyPropagateBlock()
636 if (MO.isReg() && MO.isEarlyClobber()) { in ForwardCopyPropagateBlock()
654 if (!MO.isReg()) in ForwardCopyPropagateBlock()
756 if (!MODef.isReg() || MODef.isUse()) in propagateDefs()
831 if (MO.isReg() && MO.isEarlyClobber()) { in BackwardCopyPropagateBlock()
840 if (!MO.isReg()) in BackwardCopyPropagateBlock()
H A DLiveRangeShrink.cpp142 if (!MO.isReg() || MO.isDebug()) in runOnMachineFunction()
174 if (!MO.isReg() || MO.isDead() || MO.isDebug()) in runOnMachineFunction()
235 if (MI.getOperand(0).isReg()) in runOnMachineFunction()
237 EndIter->getOperand(0).isReg() && in runOnMachineFunction()
H A DLivePhysRegs.cpp60 if (!MOP.isReg() || !MOP.readsReg()) in addUses()
84 if (O->isReg() && !O->isDebug()) { in stepForward()
106 if (Reg.second->isReg() && Reg.second->isDead()) in stepForward()
288 if (!MO->isReg() || !MO->isDef() || MO->isDebug()) in recomputeLivenessFlags()
305 if (!MO->isReg() || !MO->readsReg() || MO->isDebug()) in recomputeLivenessFlags()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
H A DLanaiDelaySlotFiller.cpp108 assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
110 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
115 RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
117 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
207 if (!MO.isReg() || !(Reg = MO.getReg())) in delayHasHazard()
236 if (!MO.isReg() || !(Reg = MO.getReg())) in insertDefsUses()
H A DLanaiMemAluCombiner.cpp185 return ((Op.isReg() && Op.getReg() == Lanai::R0) || in isZeroOperand()
247 assert((AluOffset.isReg() || AluOffset.isImm()) && in insertMergedInstruction()
264 if (AluOffset.isReg()) in insertMergedInstruction()
307 if (Offset.isReg() && Offset.getReg() == Lanai::R0) in isSuitableAluInstr()
318 } else if (Op2.isReg()) { in isSuitableAluInstr()
320 if (Offset.isReg() && Op2.getReg() == Offset.getReg()) in isSuitableAluInstr()
356 if (Offset->isReg() && InstrUsesReg(First, Offset)) in findClosestSuitableAluInstr()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp321 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg || in updateKillFlags()
374 if (!Op.isReg() || !Op.isDef()) in updateDeadsInRange()
499 if (!Op.isReg() || !DefRegs.count(Op)) in updateDeadsInRange()
582 if (SO.isReg()) { in getCondTfrOpcode()
642 if (SrcOp.isReg()) { in genCondTfrFor()
681 if (Op.isReg()) in split()
690 if (ST.isReg() && SF.isReg()) { in split()
730 if (!Op.isReg() || !Op.isDef()) in isPredicable()
766 if (!Op.isReg() || !O in getReachingDefForPred()
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H A DHexagonNewValueJump.cpp152 if (!Op.isReg() || !Op.isDef()) in canBeFeederToNewValueJump()
177 if (II->getOperand(i).isReg() && in canBeFeederToNewValueJump()
566 if (foundJump && !foundCompare && MI.getOperand(0).isReg() && in runOnMachineFunction()
573 isSecondOpReg = MI.getOperand(2).isReg(); in runOnMachineFunction()
602 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() && in runOnMachineFunction()
653 if (!MO.isReg() || !MO.isUse()) in runOnMachineFunction()
660 if (!Op.isReg() || !Op.isUse() || !Op.isKill()) in runOnMachineFunction()
706 if (cmpInstr->getOperand(0).isReg() && in runOnMachineFunction()
709 if (cmpInstr->getOperand(1).isReg() && in runOnMachineFunction()
H A DHexagonHardwareLoops.cpp341 bool isReg() const { return Kind == CV_Register; } in isReg() function in __anon24631::CountValue
345 assert(isReg() && "Wrong CountValue accessor"); in getReg()
350 assert(isReg() && "Wrong CountValue accessor"); in getSubReg()
360 if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); } in print()
677 if (Op1.isReg()) { in getLoopTripCount()
697 if (InitialValue->isReg()) { in getLoopTripCount()
707 if (EndValue->isReg()) { in getLoopTripCount()
737 if (Start->isReg()) { in computeCount()
743 if (End->isReg()) { in computeCount()
750 if (!Start->isReg() in computeCount()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.cpp71 assert(MI.getOperand(0).isReg() && MI.getOperand(1).isReg() && in loadStorePostEncoder()
119 assert(MO.isReg()); in encodeLDSTPtrReg()
140 assert(RegOp.isReg() && "Expected register operand"); in encodeMemri()
254 if (MO.isReg()) return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); in getMachineOpValue()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCCodeEmitter.cpp127 if (MO.isReg()) in getMachineOpValue()
154 if (MO.isReg() || MO.isImm()) in getCallTargetOpValue()
189 if (MO.isReg() || MO.isImm()) in getBranchTargetOpValue()
202 if (MO.isReg() || MO.isImm()) in getBranchPredTargetOpValue()
215 if (MO.isReg() || MO.isImm()) in getBranchOnRegTargetOpValue()
H A DSparcInstPrinter.cpp63 if (!MI->getOperand(0).isReg()) in printSparcAliasInstr()
87 || (!MI->getOperand(0).isReg()) in printSparcAliasInstr()
113 if (MO.isReg()) { in printOperand()
153 if (MO.isReg() && MO.getReg() == SP::G0) in printMemOperand()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
H A DNVPTXProxyRegErasure.cpp99 assert(InOp.isReg() && "ProxyReg input operand should be a register."); in replaceMachineInstructionUsage()
100 assert(OutOp.isReg() && "ProxyReg output operand should be a register."); in replaceMachineInstructionUsage()
113 if (Op.isReg() && Op.getReg() == From.getReg()) { in replaceRegisterUsage()

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