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/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_build_pm4.h76 #define radeon_set_config_reg_seq(reg, num) do { \
77 SI_CHECK_SHADOWED_REGS(reg, num); \
78 assert((reg) < SI_CONTEXT_REG_OFFSET); \
80 radeon_emit(((reg) - SI_CONFIG_REG_OFFSET) >> 2); \
83 #define radeon_set_config_reg(reg, value) do { \
84 radeon_set_config_reg_seq(reg, 1); \
88 #define radeon_set_context_reg_seq(reg, num) do { \
89 SI_CHECK_SHADOWED_REGS(reg, num); \
90 assert((reg) >= SI_CONTEXT_REG_OFFSET); \
92 radeon_emit(((reg)
[all...]
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_cs.h43 radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq() argument
45 assert(reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END); in radeon_set_config_reg_seq()
49 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2); in radeon_set_config_reg_seq()
53 radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg() argument
55 radeon_set_config_reg_seq(cs, reg, 1); in radeon_set_config_reg()
60 radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_context_reg_seq() argument
62 assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END); in radeon_set_context_reg_seq()
66 radeon_emit(cs, (reg in radeon_set_context_reg_seq()
70 radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_context_reg() argument
77 radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) radeon_set_context_reg_idx() argument
87 radeon_set_context_reg_rmw(struct radeon_cmdbuf *cs, unsigned reg, unsigned value, unsigned mask) radeon_set_context_reg_rmw() argument
98 radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) radeon_set_sh_reg_seq() argument
108 radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_sh_reg() argument
115 radeon_set_sh_reg_idx(const struct radv_physical_device *pdevice, struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) radeon_set_sh_reg_idx() argument
132 gfx10_set_sh_reg_idx3(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) gfx10_set_sh_reg_idx3() argument
143 radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) radeon_set_uconfig_reg_seq() argument
153 radeon_set_uconfig_reg_seq_perfctr(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) radeon_set_uconfig_reg_seq_perfctr() argument
163 radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_uconfig_reg() argument
170 radeon_set_uconfig_reg_idx(const struct radv_physical_device *pdevice, struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) radeon_set_uconfig_reg_idx() argument
188 radeon_set_perfctr_reg(struct radv_cmd_buffer *cmd_buffer, unsigned reg, unsigned value) radeon_set_perfctr_reg() argument
208 radeon_set_privileged_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_privileged_config_reg() argument
[all...]
/third_party/backends/backend/genesys/
H A Dgl842.cpp42 dev.reg.clear(); in gl842_init_registers()
45 dev.reg.init_reg(0x01, 0x00); in gl842_init_registers()
46 dev.reg.init_reg(0x02, 0x78); in gl842_init_registers()
47 dev.reg.init_reg(0x03, 0xbf); in gl842_init_registers()
48 dev.reg.init_reg(0x04, 0x22); in gl842_init_registers()
49 dev.reg.init_reg(0x05, 0x48); in gl842_init_registers()
51 dev.reg.init_reg(0x06, 0xb8); in gl842_init_registers()
53 dev.reg.init_reg(0x07, 0x00); in gl842_init_registers()
54 dev.reg.init_reg(0x08, 0x00); in gl842_init_registers()
55 dev.reg in gl842_init_registers()
267 gl842_init_motor_regs_scan(Genesys_Device* dev, const Genesys_Sensor& sensor, const ScanSession& session, Genesys_Register_Set* reg, const MotorProfile& motor_profile, unsigned int exposure, unsigned scan_yres, unsigned int scan_lines, unsigned int scan_dummy, unsigned int feed_steps, ScanFlag flags) gl842_init_motor_regs_scan() argument
410 gl842_init_optical_regs_scan(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set* reg, unsigned int exposure, const ScanSession& session) gl842_init_optical_regs_scan() argument
528 init_regs_for_scan_session(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set* reg, const ScanSession& session) const init_regs_for_scan_session() argument
671 begin_scan(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set* reg, bool start_motor) const begin_scan() argument
737 end_scan(Genesys_Device* dev, Genesys_Register_Set* reg, bool check_stop) const end_scan() argument
[all...]
H A Dgl846.cpp59 dev->reg.clear(); in gl846_init_registers()
61 dev->reg.init_reg(0x01, 0x60); in gl846_init_registers()
65 dev->reg.init_reg(0x01, 0x22); in gl846_init_registers()
67 dev->reg.init_reg(0x02, 0x38); in gl846_init_registers()
68 dev->reg.init_reg(0x03, 0x03); in gl846_init_registers()
72 dev->reg.init_reg(0x03, 0xbf); in gl846_init_registers()
74 dev->reg.init_reg(0x04, 0x22); in gl846_init_registers()
75 dev->reg.init_reg(0x05, 0x60); in gl846_init_registers()
79 dev->reg.init_reg(0x05, 0x48); in gl846_init_registers()
81 dev->reg in gl846_init_registers()
338 gl846_init_motor_regs_scan(Genesys_Device* dev, const Genesys_Sensor& sensor, const ScanSession& session, Genesys_Register_Set* reg, const MotorProfile& motor_profile, unsigned int scan_exposure_time, unsigned scan_yres, unsigned int scan_lines, unsigned int scan_dummy, unsigned int feed_steps, ScanFlag flags) gl846_init_motor_regs_scan() argument
514 gl846_init_optical_regs_scan(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set* reg, unsigned int exposure_time, const ScanSession& session) gl846_init_optical_regs_scan() argument
619 init_regs_for_scan_session(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set* reg, const ScanSession& session) const init_regs_for_scan_session() argument
747 begin_scan(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set* reg, bool start_motor) const begin_scan() argument
771 end_scan(Genesys_Device* dev, Genesys_Register_Set* reg, bool check_stop) const end_scan() argument
[all...]
H A Dgl124.cpp76 dev->reg.clear(); in gl124_init_registers()
79 dev->reg.init_reg(0x01, 0xa2); // + REG_0x01_SHDAREA in gl124_init_registers()
80 dev->reg.init_reg(0x02, 0x90); in gl124_init_registers()
81 dev->reg.init_reg(0x03, 0x50); in gl124_init_registers()
82 dev->reg.init_reg(0x04, 0x03); in gl124_init_registers()
83 dev->reg.init_reg(0x05, 0x00); in gl124_init_registers()
86 dev->reg.init_reg(0x06, 0x50); in gl124_init_registers()
87 dev->reg.init_reg(0x07, 0x00); in gl124_init_registers()
89 dev->reg.init_reg(0x03, 0x50 & ~REG_0x03_AVEENB); in gl124_init_registers()
90 dev->reg in gl124_init_registers()
422 gl124_init_motor_regs_scan(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set* reg, const MotorProfile& motor_profile, unsigned int scan_exposure_time, unsigned scan_yres, unsigned int scan_lines, unsigned int scan_dummy, unsigned int feed_steps, ScanColorMode scan_mode, ScanFlag flags) gl124_init_motor_regs_scan() argument
576 gl124_init_optical_regs_scan(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set* reg, unsigned int exposure_time, const ScanSession& session) gl124_init_optical_regs_scan() argument
699 init_regs_for_scan_session(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set* reg, const ScanSession& session) const init_regs_for_scan_session() argument
872 begin_scan(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set* reg, bool start_motor) const begin_scan() argument
896 end_scan(Genesys_Device* dev, Genesys_Register_Set* reg, bool check_stop) const end_scan() argument
[all...]
H A Dgl843.cpp64 dev->reg.clear(); in gl843_init_registers()
66 dev->reg.init_reg(0x01, 0x00); in gl843_init_registers()
67 dev->reg.init_reg(0x02, 0x78); in gl843_init_registers()
68 dev->reg.init_reg(0x03, 0x1f); in gl843_init_registers()
73 dev->reg.init_reg(0x03, 0x1d); in gl843_init_registers()
76 dev->reg.init_reg(0x03, 0x1c); in gl843_init_registers()
79 dev->reg.init_reg(0x04, 0x10); in gl843_init_registers()
84 dev->reg.init_reg(0x04, 0x22); in gl843_init_registers()
88 dev->reg.init_reg(0x05, 0x80); in gl843_init_registers()
93 dev->reg in gl843_init_registers()
664 gl843_init_motor_regs_scan(Genesys_Device* dev, const Genesys_Sensor& sensor, const ScanSession& session, Genesys_Register_Set* reg, const MotorProfile& motor_profile, unsigned int exposure, unsigned scan_yres, unsigned int scan_lines, unsigned int scan_dummy, unsigned int feed_steps, ScanFlag flags) gl843_init_motor_regs_scan() argument
858 gl843_init_optical_regs_scan(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set* reg, unsigned int exposure, const ScanSession& session) gl843_init_optical_regs_scan() argument
996 init_regs_for_scan_session(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set* reg, const ScanSession& session) const init_regs_for_scan_session() argument
1209 begin_scan(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set* reg, bool start_motor) const begin_scan() argument
1318 end_scan(Genesys_Device* dev, Genesys_Register_Set* reg, bool check_stop) const end_scan() argument
[all...]
/third_party/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_sanity.c67 scan_register_key(const scan_register *reg) in scan_register_key() argument
69 unsigned key = reg->file; in scan_register_key()
70 key |= (reg->indices[0] << 4); in scan_register_key()
71 key |= (reg->indices[1] << 18); in scan_register_key()
77 fill_scan_register1d(scan_register *reg, in fill_scan_register1d() argument
80 reg->file = file; in fill_scan_register1d()
81 reg->dimensions = 1; in fill_scan_register1d()
82 reg->indices[0] = index; in fill_scan_register1d()
83 reg->indices[1] = 0; in fill_scan_register1d()
87 fill_scan_register2d(scan_register *reg, in fill_scan_register2d() argument
97 scan_register_dst(scan_register *reg, struct tgsi_full_dst_register *dst) scan_register_dst() argument
115 scan_register_src(scan_register *reg, struct tgsi_full_src_register *src) scan_register_src() argument
135 scan_register *reg = MALLOC(sizeof(scan_register)); create_scan_register_src() local
144 scan_register *reg = MALLOC(sizeof(scan_register)); create_scan_register_dst() local
201 is_register_declared( struct sanity_check_ctx *ctx, const scan_register *reg) is_register_declared() argument
220 scan_register *reg = (scan_register *)cso_hash_iter_data(iter); is_any_register_declared() local
230 is_register_used( struct sanity_check_ctx *ctx, scan_register *reg) is_register_used() argument
242 is_ind_register_used( struct sanity_check_ctx *ctx, scan_register *reg) is_ind_register_used() argument
264 check_register_usage( struct sanity_check_ctx *ctx, scan_register *reg, const char *name, boolean indirect_access ) check_register_usage() argument
341 scan_register *reg = create_scan_register_dst(&inst->Dst[i]); iter_instruction() local
352 scan_register *reg = create_scan_register_src(&inst->Src[i]); iter_instruction() local
378 check_and_declare(struct sanity_check_ctx *ctx, scan_register *reg) check_and_declare() argument
423 scan_register *reg = MALLOC(sizeof(scan_register)); iter_declaration() local
431 scan_register *reg = MALLOC(sizeof(scan_register)); iter_declaration() local
436 scan_register *reg = MALLOC(sizeof(scan_register)); iter_declaration() local
455 scan_register *reg; iter_immediate() local
528 scan_register *reg = (scan_register *)cso_hash_iter_data(iter); epilog() local
550 scan_register *reg = (scan_register *)cso_hash_iter_data(iter); regs_hash_destroy() local
[all...]
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_reg.h407 struct brw_reg reg; in brw_reg() local
417 reg.type = type; in brw_reg()
418 reg.file = file; in brw_reg()
419 reg.negate = negate; in brw_reg()
420 reg.abs = abs; in brw_reg()
421 reg.address_mode = BRW_ADDRESS_DIRECT; in brw_reg()
422 reg.pad0 = 0; in brw_reg()
423 reg.subnr = subnr * type_sz(type); in brw_reg()
424 reg.nr = nr; in brw_reg()
426 /* Could do better: If the reg i in brw_reg()
[all...]
H A Dbrw_ir_fs.h39 fs_reg(struct ::brw_reg reg);
58 negate(fs_reg reg) in negate() argument
60 assert(reg.file != IMM); in negate()
61 reg.negate = !reg.negate; in negate()
62 return reg; in negate()
66 retype(fs_reg reg, enum brw_reg_type type) in retype() argument
68 reg.type = type; in retype()
69 return reg; in retype()
73 byte_offset(fs_reg reg, unsigne argument
104 horiz_offset(const fs_reg &reg, unsigned delta) horiz_offset() argument
132 offset(fs_reg reg, unsigned width, unsigned delta) offset() argument
155 component(fs_reg reg, unsigned idx) component() argument
248 is_periodic(const fs_reg &reg, unsigned n) is_periodic() argument
272 is_uniform(const fs_reg &reg) is_uniform() argument
281 quarter(const fs_reg &reg, unsigned idx) quarter() argument
[all...]
H A Dbrw_clip_tri.c53 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; in brw_clip_tri_alloc_regs()
56 c->reg.fixed_planes = brw_vec4_grf(i, 0); in brw_clip_tri_alloc_regs()
68 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_clip_tri_alloc_regs()
79 brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0)); in brw_clip_tri_alloc_regs()
83 c->reg.t = brw_vec1_grf(i, 0); in brw_clip_tri_alloc_regs()
84 c->reg.loopcount = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_D); in brw_clip_tri_alloc_regs()
85 c->reg.nr_verts = retype(brw_vec1_grf(i, 2), BRW_REGISTER_TYPE_UD); in brw_clip_tri_alloc_regs()
86 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); in brw_clip_tri_alloc_regs()
87 c->reg.plane_equation = brw_vec4_grf(i, 4); in brw_clip_tri_alloc_regs()
90 c->reg in brw_clip_tri_alloc_regs()
[all...]
H A Dbrw_clip_line.c46 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; in brw_clip_line_alloc_regs()
49 c->reg.fixed_planes = brw_vec4_grf(i, 0); in brw_clip_line_alloc_regs()
61 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_clip_line_alloc_regs()
65 c->reg.t = brw_vec1_grf(i, 0); in brw_clip_line_alloc_regs()
66 c->reg.t0 = brw_vec1_grf(i, 1); in brw_clip_line_alloc_regs()
67 c->reg.t1 = brw_vec1_grf(i, 2); in brw_clip_line_alloc_regs()
68 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); in brw_clip_line_alloc_regs()
69 c->reg.plane_equation = brw_vec4_grf(i, 4); in brw_clip_line_alloc_regs()
72 c->reg.dp0 = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ in brw_clip_line_alloc_regs()
73 c->reg in brw_clip_line_alloc_regs()
[all...]
H A Dbrw_compile_ff_gs.c64 } reg; member
90 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; in brw_ff_gs_alloc_regs()
94 c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); in brw_ff_gs_alloc_regs()
99 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_ff_gs_alloc_regs()
103 c->reg.header = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); in brw_ff_gs_alloc_regs()
104 c->reg.temp = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); in brw_ff_gs_alloc_regs()
107 c->reg.destination_indices = in brw_ff_gs_alloc_regs()
117 * Set up the initial value of c->reg.header register based on c->reg.R0.
133 brw_MOV(p, c->reg in brw_ff_gs_initialize_header()
[all...]
H A Dbrw_ir_vec4.h43 src_reg(struct ::brw_reg reg);
51 explicit src_reg(const dst_reg &reg);
57 retype(src_reg reg, enum brw_reg_type type) in retype() argument
59 reg.type = type; in retype()
60 return reg; in retype()
66 add_byte_offset(backend_reg *reg, unsigned bytes) in add_byte_offset() argument
68 switch (reg->file) { in add_byte_offset()
74 reg->offset += bytes; in add_byte_offset()
75 assert(reg->offset % 16 == 0); in add_byte_offset()
78 const unsigned suboffset = reg in add_byte_offset()
100 byte_offset(src_reg reg, unsigned bytes) byte_offset() argument
107 offset(src_reg reg, unsigned width, unsigned delta) offset() argument
115 horiz_offset(src_reg reg, unsigned delta) horiz_offset() argument
125 swizzle(src_reg reg, unsigned swizzle) swizzle() argument
136 negate(src_reg reg) negate() argument
144 is_uniform(const src_reg &reg) is_uniform() argument
174 retype(dst_reg reg, enum brw_reg_type type) retype() argument
181 byte_offset(dst_reg reg, unsigned bytes) byte_offset() argument
188 offset(dst_reg reg, unsigned width, unsigned delta) offset() argument
196 horiz_offset(const dst_reg &reg, unsigned delta) horiz_offset() argument
205 writemask(dst_reg reg, unsigned mask) writemask() argument
[all...]
/third_party/libunwind/libunwind/src/arm/
H A DGstash_frame.c39 rs->reg.where[DWARF_CFA_REG_COLUMN], in tdep_stash_frame()
40 rs->reg.val[DWARF_CFA_REG_COLUMN], in tdep_stash_frame()
41 rs->reg.val[DWARF_CFA_OFF_COLUMN], in tdep_stash_frame()
43 rs->reg.where[R7], rs->reg.val[R7], DWARF_GET_LOC(d->loc[R7]), in tdep_stash_frame()
44 rs->reg.where[LR], rs->reg.val[LR], DWARF_GET_LOC(d->loc[LR]), in tdep_stash_frame()
45 rs->reg.where[SP], rs->reg.val[SP], DWARF_GET_LOC(d->loc[SP])); in tdep_stash_frame()
54 && (rs->reg in tdep_stash_frame()
[all...]
/third_party/libunwind/libunwind/src/aarch64/
H A DGstash_frame.c39 rs->reg.where[DWARF_CFA_REG_COLUMN], in tdep_stash_frame()
40 rs->reg.val[DWARF_CFA_REG_COLUMN], in tdep_stash_frame()
41 rs->reg.val[DWARF_CFA_OFF_COLUMN], in tdep_stash_frame()
43 rs->reg.where[FP], rs->reg.val[FP], DWARF_GET_LOC(d->loc[FP]), in tdep_stash_frame()
44 rs->reg.where[LR], rs->reg.val[LR], DWARF_GET_LOC(d->loc[LR]), in tdep_stash_frame()
45 rs->reg.where[SP], rs->reg.val[SP], DWARF_GET_LOC(d->loc[SP])); in tdep_stash_frame()
54 && (rs->reg in tdep_stash_frame()
[all...]
/third_party/mesa3d/src/panfrost/bifrost/test/
H A Dtest-optimizer.cpp46 reg = bi_register(0); in Optimizer()
58 bi_index reg; member in Optimizer
66 CASE(bi_fadd_f32_to(b, reg, bi_fabsneg_f32(b, bi_abs(x)), y), in TEST_F()
67 bi_fadd_f32_to(b, reg, bi_abs(x), y)); in TEST_F()
69 CASE(bi_fadd_f32_to(b, reg, bi_fabsneg_f32(b, bi_neg(x)), y), in TEST_F()
70 bi_fadd_f32_to(b, reg, bi_neg(x), y)); in TEST_F()
72 CASE(bi_fadd_f32_to(b, reg, bi_fabsneg_f32(b, negabsx), y), in TEST_F()
73 bi_fadd_f32_to(b, reg, negabsx, y)); in TEST_F()
75 CASE(bi_fadd_f32_to(b, reg, bi_fabsneg_f32(b, x), y), in TEST_F()
76 bi_fadd_f32_to(b, reg, in TEST_F()
[all...]
/third_party/lzma/Asm/arm64/
H A D7zAsm.S41 .macro p2_add reg:req, param:req
42 add \reg, \reg, \param
45 .macro p2_sub reg:req, param:req
46 sub \reg, \reg, \param
49 .macro p2_sub_s reg:req, param:req
50 subs \reg, \reg, \param
53 .macro p2_and reg
[all...]
/third_party/mesa3d/src/panfrost/bifrost/valhall/test/
H A Dtest-lower-isel.cpp45 reg = bi_register(1); in LowerIsel()
56 bi_index reg, x, y, z; member in LowerIsel
61 CASE(bi_swz_v4i8_to(b, reg, bi_byte(reg, i)), in TEST_F()
62 bi_iadd_v4u8_to(b, reg, bi_byte(reg, i), bi_zero(), false)); in TEST_F()
69 CASE(bi_swz_v2i16_to(b, reg, bi_swz_16(reg, i, j)), in TEST_F()
70 bi_iadd_v2u16_to(b, reg, bi_swz_16(reg, in TEST_F()
[all...]
/third_party/musl/porting/linux/user/include/sys/
H A Dsspret.h22 # define SSPRET_CALC_RETCOOKIE(reg) \
23 eor reg, reg, x30
25 # define SSPRET_LOAD_COOKIE(x, reg) \
26 mov reg, x29
28 # define SSPRET_SETUP(x, reg) \
29 SSPRET_LOAD_COOKIE(x, reg); \
30 SSPRET_CALC_RETCOOKIE(reg)
32 # define SSPRET_CHECK(x, reg) \
35 subs reg, re
[all...]
/third_party/musl/include/sys/linux/
H A Dsspret.h21 # define SSPRET_CALC_RETCOOKIE(reg) \
22 eor reg, reg, x30
24 # define SSPRET_LOAD_COOKIE(x, reg) \
25 mov reg, x29
27 # define SSPRET_SETUP(x, reg) \
28 SSPRET_LOAD_COOKIE(x, reg); \
29 SSPRET_CALC_RETCOOKIE(reg)
31 # define SSPRET_CHECK(x, reg) \
34 subs reg, re
[all...]
/third_party/libunwind/libunwind/src/x86_64/
H A DGstash_frame.c37 rs->reg.where[DWARF_CFA_REG_COLUMN], in tdep_stash_frame()
38 rs->reg.val[DWARF_CFA_REG_COLUMN], in tdep_stash_frame()
39 rs->reg.val[DWARF_CFA_OFF_COLUMN], in tdep_stash_frame()
41 rs->reg.where[RBP], rs->reg.val[RBP], DWARF_GET_LOC(d->loc[RBP]), in tdep_stash_frame()
42 rs->reg.where[RSP], rs->reg.val[RSP], DWARF_GET_LOC(d->loc[RSP])); in tdep_stash_frame()
44 if (rs->reg.where[DWARF_CFA_REG_COLUMN] == DWARF_WHERE_EXPR && in tdep_stash_frame()
45 rs->reg.where[RBP] == DWARF_WHERE_EXPR) { in tdep_stash_frame()
49 unw_word_t cfa_addr = rs->reg in tdep_stash_frame()
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/third_party/mesa3d/src/gallium/drivers/i915/
H A Di915_fpc_emit.c47 i915_release_temp(struct i915_fp_compile *p, int reg) in i915_release_temp() argument
49 p->temp_flag &= ~(1 << reg); in i915_release_temp()
79 uint32_t reg = UREG(type, nr); in i915_emit_decl() local
83 return reg; in i915_emit_decl()
88 return reg; in i915_emit_decl()
92 return reg; in i915_emit_decl()
95 *(p->decl++) = (D0_DCL | D0_DEST(reg) | d0_flags); in i915_emit_decl()
102 return reg; in i915_emit_decl()
200 temp = i915_get_temp(p); /* get temp reg index */ in i915_emit_texld()
204 A0_DEST_CHANNEL_ALL, /* dest reg, writemas in i915_emit_texld()
261 unsigned reg, idx; i915_emit_const1f() local
291 unsigned reg, idx; i915_emit_const2f() local
330 unsigned reg; i915_emit_const4f() local
[all...]
/third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/
H A Dir2_ra.c59 struct ir2_reg *reg; in set_need_emit() local
74 reg = get_reg_src(ctx, src); in set_need_emit()
76 if (!instr->is_ssa && instr->reg == reg) in set_need_emit()
110 struct ir2_reg *reg; in ra_count_refs() local
132 reg = get_reg_src(ctx, src); in ra_count_refs()
134 reg->comp[swiz_get(src->swizzle, i)].ref_count++; in ra_count_refs()
140 ra_reg(struct ir2_context *ctx, struct ir2_reg *reg, int force_idx, bool export, in ra_reg() argument
146 reg->comp[i].c = i; in ra_reg()
158 for (int i = 0; i < reg in ra_reg()
199 struct ir2_reg *reg; ra_src_free() local
[all...]
/third_party/libunwind/libunwind/src/ia64/
H A DGregs.c31 linux_scratch_loc (struct cursor *c, unw_regnum_t reg, uint8_t *nat_bitnr) in linux_scratch_loc() argument
40 switch (reg) in linux_scratch_loc()
46 *nat_bitnr = (reg - UNW_IA64_NAT); in linux_scratch_loc()
52 addr += LINUX_SC_GR_OFF + 8 * (reg - UNW_IA64_GR); in linux_scratch_loc()
56 addr += LINUX_SC_FR_OFF + 16 * (reg - UNW_IA64_FR); in linux_scratch_loc()
78 addr += LINUX_SC_FR_OFF + 16 * (reg - UNW_IA64_FR); in linux_scratch_loc()
90 if (unw_is_fpreg (reg)) in linux_scratch_loc()
91 return IA64_FPREG_LOC (c, reg); in linux_scratch_loc()
93 return IA64_REG_LOC (c, reg); in linux_scratch_loc()
101 if ((unsigned) (reg in linux_scratch_loc()
223 hpux_scratch_loc(struct cursor *c, unw_regnum_t reg, uint8_t *nat_bitnr) hpux_scratch_loc() argument
233 ia64_scratch_loc(struct cursor *c, unw_regnum_t reg, uint8_t *nat_bitnr) ia64_scratch_loc() argument
360 tdep_access_reg(struct cursor *c, unw_regnum_t reg, unw_word_t *valp, int write) tdep_access_reg() argument
562 tdep_access_fpreg(struct cursor *c, int reg, unw_fpreg_t *valp, int write) tdep_access_fpreg() argument
[all...]
/third_party/node/deps/v8/src/wasm/baseline/
H A Dliftoff-register.h150 constexpr explicit LiftoffRegister(Register reg) in LiftoffRegister() argument
151 : LiftoffRegister(reg.code()) { in LiftoffRegister()
152 DCHECK(kLiftoffAssemblerGpCacheRegs.has(reg)); in LiftoffRegister()
153 DCHECK_EQ(reg, gp()); in LiftoffRegister()
155 constexpr explicit LiftoffRegister(DoubleRegister reg) in LiftoffRegister() argument
156 : LiftoffRegister(kAfterMaxLiftoffGpRegCode + reg.code()) { in LiftoffRegister()
157 DCHECK(kLiftoffAssemblerFpCacheRegs.has(reg)); in LiftoffRegister()
158 DCHECK_EQ(reg, fp()); in LiftoffRegister()
162 LiftoffRegister reg{static_cast<storage_t>(code)}; in from_liftoff_code()
164 // reg in from_liftoff_code()
317 operator <<(std::ostream& os, LiftoffRegister reg) operator <<() argument
361 set(Register reg) set() argument
364 set(DoubleRegister reg) set() argument
368 set(LiftoffRegister reg) set() argument
378 clear(LiftoffRegister reg) clear() argument
387 clear(Register reg) clear() argument
390 clear(DoubleRegister reg) clear() argument
519 LiftoffRegister reg = reglist.GetFirstRegSet(); operator <<() local
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